Information

PIC18F8722 FAMILY

19.4.4.5 Clock Synchronization and

the CKP bit

When the CKP bit is cleared, the SCLx output is forced

to ‘0’. However, clearing the CKP bit will not assert the

SCLx output low until the SCLx output is already

sampled low. Therefore, the CKP bit will not assert the

SCLx line until an external I

C master device has

already asserted the SCLx line. The SCLx output will

remain low until the CKP bit is set and all other

devices on the I

C bus have deasserted SCLx. This

ensures that a write to the CKP bit will not violate the

minimum high time requirement for SCLx (see

Figure 19-12).

FIGURE 19-12: CLOCK SYNCHRONIZATION TIMING

SDAx

SCLx

DX – 1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SSPxCON1

CKP

Master device

deasserts clock

Master device

asserts clock