Information

PIC18F8722 FAMILY
DS39646C-page 224 © 2008 Microchip Technology Inc.
FIGURE 19-11: I
2
C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
SDAx SCLx SSPxIF (PIR1<3> or PIR3<7>) BF (SSPxSTAT<0>)
S
123456789 123456789 12345 7 89
P
1 1 1 1 0 A9A8 A7 A6A5A4A3A2A1A0 1 1 1 1 0 A8
R/W = 1
ACK
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in software
Bus master
terminates transfer
A9
6
Receive Second Byte of Address
Cleared by hardware when SSPxADD is updated with low byte of address
UA (SSPxSTAT<1>)
Clock is held low until update of SSPxADD has taken place
UA is set indicating that the SSPxADD needs to be updated
UA is set indicating that SSPxADD needs to be updated
Cleared by hardware when SSPxADD is updated with high byte of address.
SSPxBUF is written with contents of SSPxSR
Dummy read of SSPxBUF to clear BF flag
Receive First Byte of Address
12345 789
D7 D6 D5 D4 D3 D1
ACK
D2
6
Transmitting Data Byte
D0
Dummy read of SSPxBUF to clear BF flag
Sr
Cleared in software
Write of SSPxBUF
initiates transmit
Cleared in software
Completion of clears BF flag
CKP (SSPxCON1<4>)
CKP is set in software
CKP is automatically cleared in hardware, holding SCLx low
Clock is held low until update of SSPxADD has taken place
data transmission
Clock is held low until CKP is set to ‘
1’
third address sequence BF flag is clear at the end of the