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PIC18F8722 FAMILY
DS39646C-page 220 © 2008 Microchip Technology Inc.
19.4.3.2 Reception
When the R/W bit of the address byte is clear and an
address match occurs, the R/W
bit of the SSPxSTAT
register is cleared. The received address is loaded into
the SSPxBUF register and the SDAx line is held low
(ACK
).
When the address byte overflow condition exists, then
the no Acknowledge (ACK
) pulse is given. An overflow
condition is defined as either bit BF (SSPxSTAT<0>) is
set, or bit SSPOV (SSPxCON1<6>) is set.
An MSSP interrupt is generated for each data transfer
byte. The interrupt flag bit, SSPxIF, must be cleared in
software. The SSPxSTAT register is used to determine
the status of the byte.
If SEN is enabled (SSPxCON2<0> = 1), SCLx will be
held low (clock stretch) following each data transfer. The
clock must be released by setting bit, CKP
(SSPxCON1<4>). See Section 19.4.4 “Clock
Stretching” for more detail.
19.4.3.3 Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W
bit of the
SSPxSTAT register is set. The received address is
loaded into the SSPxBUF register. The ACK pulse will
be sent on the ninth bit and pin SCLx is held low regard-
less of SEN (see Section 19.4.4 “Clock Stretching”
for more detail). By stretching the clock, the master will
be unable to assert another clock pulse until the slave
is done preparing the transmit data. The transmit data
must be loaded into the SSPxBUF register which also
loads the SSPxSR register. Then pin SCLx should be
enabled by setting bit, CKP (SSPxCON1<4>). The
eight data bits are shifted out on the falling edge of the
SCLx input. This ensures that the SDAx signal is valid
during the SCLx high time (Figure 19-9).
The ACK
pulse from the master-receiver is latched on
the rising edge of the ninth SCLx input pulse. If the
SDAx line is high (not ACK), then the data transfer is
complete. In this case, when the ACK
is latched by the
slave, the slave logic is reset (resets SSPxSTAT
register) and the slave monitors for another occurrence
of the Start bit. If the SDAx line was low (ACK
), the next
transmit data must be loaded into the SSPxBUF
register. Again, pin SCLx must be enabled by setting bit
CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPxIF bit must be cleared in software and
the SSPxSTAT register is used to determine the status
of the byte. The SSPxIF bit is set on the falling edge of
the ninth clock pulse.