Information

PIC18F8722 FAMILY
DS39646C-page 20 © 2008 Microchip Technology Inc.
PORTG is a bidirectional I/O port.
RG0/ECCP3/P3A
RG0
ECCP3
P3A
3
I/O
I/O
O
ST
ST
—
Digital I/O.
Enhanced Capture 3 input/Compare 3 output/
PWM 3 output.
ECCP3 PWM output A.
RG1/TX2/CK2
RG1
TX2
CK2
4
I/O
O
I/O
ST
—
ST
Digital I/O.
EUSART2 asynchronous transmit.
EUSART2 synchronous clock (see related RX2/DT2).
RG2/RX2/DT2
RG2
RX2
DT2
5
I/O
I
I/O
ST
ST
ST
Digital I/O.
EUSART2 asynchronous receive.
EUSART2 synchronous data (see related TX2/CK2).
RG3/CCP4/P3D
RG3
CCP4
P3D
6
I/O
I/O
O
ST
ST
—
Digital I/O.
Capture 4 input/Compare 4 output/PWM 4 output.
ECCP3 PWM output D.
RG4/CCP5/P1D
RG4
CCP5
P1D
8
I/O
I/O
O
ST
ST
—
Digital I/O.
Capture 5 input/Compare 5 output/PWM 5 output.
ECCP1 PWM output D.
RG5 See RG5/MCLR
/VPP pin.
V
SS 9, 25, 41, 56 P — Ground reference for logic and I/O pins.
VDD 10, 26, 38, 57 P — Positive supply for logic and I/O pins.
AVSS 20 P — Ground reference for analog modules.
AV
DD 19 P — Positive supply for analog modules.
TABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog= Analog input
I = Input O = Output
P= Power I
2
C™ = I
2
C/SMBus input buffer
Note 1: Default assignment for ECCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared.