Information

© 2008 Microchip Technology Inc. DS39646C-page 215
PIC18F8722 FAMILY
19.4 I
2
C Mode
The MSSP module in I
2
C mode fully implements all
master and slave functions (including general call
support) and provides interrupts on Start and Stop bits
in hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer:
• Serial clock (SCLx) – RC3/SCK1/SCL1 or
RD6/SCK2/SCL2
• Serial data (SDAx) – RC4/SDI1/SDA1 or
RD5/SDI2/SDA2
The user must configure these pins as inputs by setting
the associated TRIS bits.
FIGURE 19-7: MSSP BLOCK DIAGRAM
(I
2
C™ MODE)
Read Write
SSPxSR reg
Match Detect
SSPxADD reg
SSPxBUF reg
Internal
Data Bus
Addr Match
Set, Reset
S, P bits
(SSPxSTAT reg)
RC3 or
RC4 or
Shift
Clock
MSb
LSb
Note: Only port I/O names are used in this diagram for
the sake of brevity. Refer to the text for a full list of
multiplexed functions.
RD6
RD5
Start and
Stop bit Detect