Information

© 2008 Microchip Technology Inc. DS39646C-page 193
PIC18F8722 FAMILY
FIGURE 18-1: SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE
18.4.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The PWM duty cycle is
calculated by the equation:
EQUATION 18-2:
CCPR1L and CCP1CON<5:4> can be written to at any
time but the duty cycle value is not copied into
CCPR1H until a match between PR2 and TMR2 occurs
(i.e., the period is complete). In PWM mode, CCPR1H
is a read-only register.
The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM opera-
tion. When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or two bits
of the TMR2 prescaler, the ECCP1 pin is cleared. The
maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:
EQUATION 18-3:
TABLE 18-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
CCPR1L
CCPR1H (Slave)
Comparator
TMR2
Comparator
PR2
(Note 1)
RQ
S
Duty Cycle Registers
CCP1CON<5:4>
Clear Timer,
set ECCP1 pin and
latch D.C.
Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base.
TRISx<x>
ECCP1/P1A
TRISx<x>
P1B
TRISx<x>
TRISx<x>
P1D
Output
Controller
P1M1<1:0>
2
CCP1M<3:0>
4
ECCP1DEL
ECCP1/P1A
P1B
P1C
P1D
P1C
PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) •
T
OSC • (TMR2 Prescale Value)
Note: If the PWM duty cycle value is longer than
the PWM period, the ECCP1 pin will not
be cleared.
(
)
PWM Resolution (max) =
F
OSC
FPWM
log
log(2)
bits
PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16)1641111
PR2 Value FFh FFh FFh 3Fh 1Fh 17h
Maximum Resolution (bits) 10 10 10 8 7 6.58