Information

© 2008 Microchip Technology Inc. DS39646C-page 179
PIC18F8722 FAMILY
17.0 CAPTURE/COMPARE/PWM
(CCP) MODULES
The PIC18F8722 family of devices all have a total of
five CCP (Capture/Compare/PWM) modules. Two of
these (CCP4 and CCP5) implement standard Capture,
Compare and Pulse-Width Modulation (PWM) modes
and are discussed in this section. The other three
modules (ECCP1, ECCP2, ECCP3) implement
standard Capture and Compare modes, as well as
Enhanced PWM modes. These are discussed in
Section 18.0 “Enhanced Capture/Compare/PWM
(ECCP) Module”.
Each CCP/ECCP module contains a 16-bit register
which can operate as a 16-bit Capture register, a 16-bit
Compare register or a PWM Master/Slave Duty Cycle
register. For the sake of clarity, all CCP module opera-
tions in the following sections are described with
respect to CCP4, but are equally applicable to CCP5.
Capture and Compare operations described in this chap-
ter apply to all standard and Enhanced CCP modules.
The operations of PWM mode described in Section 17.4
“PWM Mode” apply to CCP4 and CCP5 only.
Note: Throughout this section and Section 18.0
“Enhanced Capture/Compare/PWM
(ECCP) Module”, references to register
and bit names that may be associated with
a specific CCP module are referred to
generically by the use of ‘x’ or ‘y’ in place of
the specific module number. Thus,
“CCPxCON” might refer to the control
register for CCP4 or CCP5, or ECCP1,
ECCP2 or ECCP3. “CCPxCON” is used
throughout these sections to refer to the
module control register, regardless of
whether the CCP module is a standard or
enhanced implementation.
REGISTER 17-1: CCPxCON: CCPx CONTROL REGISTER (CCP4 AND CCP5 MODULES)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 DCxB<1:0>: PWM Duty Cycle bit 1 and bit 0 for CCP Module x
Capture mode:
Unused.
Compare mode
:
Unused.
PWM mode:
These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight
Most Significant bits (DCx<9:2>) of the duty cycle are found in CCPRxL.
bit 3-0 CCPxM<3:0>: CCP Module x Mode Select bits
0000 = Capture/Compare/PWM disabled; resets CCPx module
0001 = Reserved
0010 = Compare mode, toggle output on match; CCPxIF bit is set
0011 = Reserved
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, initialize CCPx pin low; on compare match, force CCPx pin high; CCPxIF bit is set
1001 = Compare mode, initialize CCPx pin high; on compare match, force CCPx pin low; CCPxIF bit is set
1010 = Compare mode, generate software interrupt on compare match; CCPxIF bit is set; CCPx pin
reflects I/O state
1011 = Compare mode, trigger special event; CCPxIF bit is set, CCPx pin is unaffected (For the effects
of the trigger, see Section 17.3.4 “Special Event Trigger”.)
11xx = PWM mode