Information

© 2008 Microchip Technology Inc. DS39646C-page 155
PIC18F8722 FAMILY
TABLE 11-15: PORTH FUNCTIONS
TABLE 11-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH
Pin Name Function
TRIS
Setting
I/O
I/O
Type
Description
RH0/A16 RH0 0 O DIG LATH<0> data output.
1 I ST PORTH<0> data input.
A16 x O DIG External memory interface, address line 16. Takes priority over port data.
RH1/A17 RH1 0 O DIG LATH<1> data output.
1 I ST PORTH<1> data input.
A17 x O DIG External memory interface, address line 17. Takes priority over port data.
RH2/A18 RH2 0 O DIG LATH<2> data output.
1 I ST PORTH<2> data input.
A18 x O DIG External memory interface, address line 18. Takes priority over port data.
RH3/A19 RH3 0 O DIG LATH<3> data output.
1 I ST PORTH<3> data input.
A19 x O DIG External memory interface, address line 19. Takes priority over port data.
RH4/AN12/
P3C
RH4 0 O DIG LATH<4> data output.
1 I ST PORTH<4> data input.
AN12 1 I ANA A/D input channel 12. Default configuration on POR.
P3C
(1)
0 O DIG ECCP3 Enhanced PWM output, channel C. May be configured for tri-state
during Enhanced PWM shutdown events. Takes priority over port data.
RH5/AN13/
P3B
RH5 0 O DIG LATH<5> data output.
1 I ST PORTH<5> data input.
AN13 1 I ANA A/D input channel 13. Default configuration on POR.
P3B
(1)
0 O DIG ECCP3 Enhanced PWM output, channel B. May be configured for tri-state
during Enhanced PWM shutdown events. Takes priority over port data.
RH6/AN14/
P1C
RH6 0 O DIG LATH<6> data output.
1 I ST PORTH<6> data input.
AN14 1 I ANA A/D input channel 14. Default configuration on POR.
P1C
(1)
0 O DIG ECCP1 Enhanced PWM output, channel C. May be configured for tri-state
during Enhanced PWM shutdown events. Takes priority over port data.
RH7/AN15/
P1B
RH7 0 O DIG LATH<7> data output.
1 I ST PORTH<7> data input.
AN15 1 I ANA A/D input channel 15. Default configuration on POR.
P1B
(1)
0 O DIG ECCP1 Enhanced PWM output, channel B. May be configured for tri-state
during Enhanced PWM shutdown events. Takes priority over port data.
Legend: PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
TRISH TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 60
PORTH RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 60
LATH LATH7 LATH6 LATH5 LATH4 LATH3 LATH2 LATH1 LATH0 60
ADCON1
— — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 59