Information
PIC18F8722 FAMILY
DS39646C-page 148 © 2008 Microchip Technology Inc.
TABLE 11-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
RE5/AD13/P1C RE5 0 O DIG LATE<5> data output.
1 I ST PORTE<5> data input.
AD13
(2)
x O DIG External memory interface, address/data bit 13 output. Takes priority
over ECCP and port data.
x I TTL External memory interface, data bit 13 input.
P1C 0 O DIG ECCP1 Enhanced PWM output, channel C. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
RE6/AD14/P1B RE6 0 O DIG LATE<6> data output.
1 I ST PORTE<6> data input.
AD14
(2)
x O DIG External memory interface, address/data bit 14 output. Takes priority
over ECCP and port data.
x I TTL External memory interface, data bit 14 input.
P1B 0 O DIG ECCP1 Enhanced PWM output, channel B. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
RE7/AD15/
ECCP2/P2A
RE7 0 O DIG LATE<7> data output.
1 I ST PORTE<7> data input.
AD15
(2)
x O DIG External memory interface, address/data bit 15 output. Takes priority
over ECCP and port data.
x I TTL External memory interface, data bit 15 input.
ECCP2
(1)
0 O DIG ECCP2 compare output and ECCP2 PWM output. Takes priority over
port data.
1 I ST ECCP2 capture input.
P2A
(1)
0 O DIG ECCP2 Enhanced PWM output, channel A. Takes priority over port and
data. May be configured for tri-state during Enhanced PWM shutdown
events.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 60
LATE LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 60
TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 60
TABLE 11-9: PORTE FUNCTIONS (CONTINUED)
Pin Name Function
TRIS
Setting
I/O
I/O
Type
Description
Legend: PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Alternate assignment for ECCP2 when CCP2MX Configuration bit is cleared (all devices in Microcontroller mode).
2: Implemented on 80-pin devices only.