Information

© 2008 Microchip Technology Inc. DS39646C-page 147
PIC18F8722 FAMILY
TABLE 11-9: PORTE FUNCTIONS
Pin Name Function
TRIS
Setting
I/O
I/O
Type
Description
RE0/AD8/
RD
/P2D
RE0 0 O DIG LATE<0> data output.
1 I ST PORTE<0> data input.
AD8
(2)
x O DIG External memory interface, address/data bit 8 output. Takes priority
over ECCP and port data.
x I TTL External memory interface, data bit 8 input.
RD
1 I TTL Parallel Slave Port read enable control input.
P2D 0 O DIG ECCP2 Enhanced PWM output, channel D. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
RE1/AD9/
WR
/P2C
RE1 0 O DIG LATE<1> data output.
1 I ST PORTE<1> data input.
AD9
(2)
x O DIG External memory interface, address/data bit 9 output. Takes priority
over ECCP and port data.
x I TTL External memory interface, data bit 9 input.
WR
1 I TTL Parallel Slave Port write enable control input.
P2C 0 O DIG ECCP2 Enhanced PWM output, channel C. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
RE2/AD10/
CS
/P2B
RE2 0 O DIG LATE<2> data output.
1 I ST PORTE<2> data input.
AD10
(2)
x O DIG External memory interface, address/data bit 10 output. Takes priority
over ECCP and port data.
x I TTL External memory interface, data bit 10 input.
CS
1 I TTL Parallel Slave Port chip select control input.
P2B 0 O DIG ECCP2 Enhanced PWM output, channel B. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
RE3/AD11/P3C RE3 0 O DIG LATE<3> data output.
1 I ST PORTE<3> data input.
AD11
(2)
x O DIG External memory interface, address/data bit 11 output. Takes priority
over ECCP and port data.
x I TTL External memory interface, data bit 11 input.
P3C 0 O DIG ECCP3 Enhanced PWM output, channel C. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
RE4/AD12/P3B RE4 0 O DIG LATE<4> data output.
1 I ST PORTE<4> data input.
AD12
(2)
x O DIG External memory interface, address/data bit 12 output. Takes priority
over ECCP and port data.
x I TTL External memory interface, data bit 12 input.
P3B 0 O DIG ECCP3 Enhanced PWM output, channel B. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
Legend: PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Alternate assignment for ECCP2 when CCP2MX Configuration bit is cleared (all devices in Microcontroller mode).
2: Implemented on 80-pin devices only.