Information

© 2008 Microchip Technology Inc. DS39646C-page 137
PIC18F8722 FAMILY
11.2 PORTB, TRISB and
LATB Registers
PORTB is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISB bit (= 0)
will make the corresponding PORTB pin an output
(i.e., put the contents of the output latch on the
selected pin).
The Data Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register read and write the latched output value for
PORTB.
EXAMPLE 11-2: INITIALIZING PORTB
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
Four of the PORTB pins (RB<7:4>) have an
interrupt-on-change feature. Only pins configured as
inputs can cause this interrupt to occur (i.e., any
RB7:RB4 pin configured as an output is excluded from
the interrupt-on-change comparison). The input pins (of
RB7:RB4) are compared with the old value latched on
the last read of PORTB. The “mismatch” outputs of
RB7:RB4 are ORed together to generate the RB Port
Change Interrupt with Flag bit, RBIF (INTCON<0>).
This interrupt can wake the device from
power-managed modes. The user, in the Interrupt
Service Routine, can clear the interrupt in the following
manner:
a) Any read or write of PORTB (except with the
MOVSF, MOVSS, MOVFF (ANY), PORTB
instruction). This will end the mismatch
condition.
b) Clear flag bit, RBIF.
A mismatch condition will continue to set flag bit, RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit, RBIF, to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
For 80-pin devices, RB3 can be configured as the
alternate peripheral pin for the ECCP2 module by
clearing the CCP2MX Configuration bit. This applies
only when the device is in one of the operating modes
other than the default Microcontroller mode. If the
device is in Microcontroller mode, the alternate
assignment for ECCP2 is RE7. As with other ECCP2
configurations, the user must ensure that the
TRISB<3> bit is set appropriately for the intended
operation.
CLRF PORTB ; Initialize PORTB by
; clearing output
; data latches
CLRF LATB ; Alternate method
; to clear output
; data latches
MOVLW 0CFh ; Value used to
; initialize data
; direction
MOVWF TRISB ; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs