Information

PIC18F8722 FAMILY
DS39646C-page 132 © 2008 Microchip Technology Inc.
REGISTER 10-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SSP2IP: MSSP2 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6 BCL2IP: MSSP2 Bus Collision Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5 RC2IP: EUSART2 Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4 TX2IP: EUSART2 Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3 TMR4IP: TMR4 to PR4 Match Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2 CCP5IP: CCP5 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 CCP4IP: CCP4 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0 CCP3IP: ECCP3 Interrupt Priority bit
1 = High priority
0 = Low priority