Information

PIC18F8722 FAMILY
DS39646C-page 104 © 2008 Microchip Technology Inc.
7.5.4 16-BIT MODE TIMING
The presentation of control signals on the External
Memory Bus is different for the various operating
modes. Typical signal timing diagrams are shown in
Figure 7-4 through Figure 7-6. All examples assume
either 20-bit or 21-bit address widths.
FIGURE 7-4: EXTERNAL MEMORY BUS TIMING FOR TBLRD WITH A 1 TCY WAIT STATE
(MICROPROCESSOR MODE)
FIGURE 7-5: EXTERNAL MEMORY BUS TIMING FOR TBLRD
(EXTENDED MICROCONTROLLER MODE)
Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q4Q4 Q4 Q4
ALE
OE
3AABh
WRH
WRL
AD<15:0>
BA0
CF33h
Opcode Fetch
MOVLW 55h
from 007556h
9256h
0E55h
‘1’ ‘1’
‘1’
‘1’
Table Read
of 92h
from 199E67h
1 T
CY Wait
Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4
Apparent Q
Actual Q
A<19:16>
CE
‘0’
‘0’
Memory
Cycle
Instruction
Execution
TBLRD Cycle 1
TBLRD Cycle 2
0Ch
00h
Q2Q1 Q3 Q4 Q2Q1 Q3 Q4
Q2Q1 Q3 Q4
A<19:16>
ALE
OE
AD<15:0>
CE
Opcode Fetch Opcode Fetch Opcode Fetch
TBLRD *
TBLRD Cycle 1
ADDLW 55h
from 000100h
Q2Q1 Q3 Q4
0Ch
CF33h
TBLRD 92h
from 199E67h
9256h
from 000104h
Memory
Cycle
Instruction
Execution
INST(PC – 2)
TBLRD Cycle 2
MOVLW 55h
from 000102h
MOVLW