Datasheet

PIC32MX3XX/4XX

SPI2E – SPI2 Fault 37 31 IFS1<5> IEC1<5> IPC7<28:26> IPC7<25:24>

SPI2TX – SPI2 Transfer Done 38 31 IFS1<6> IEC1<6> IPC7<28:26> IPC7<25:24>

SPI2RX – SPI2 Receive Done 39 31 IFS1<7> IEC1<7> IPC7<28:26> IPC7<25:24>

U2E – UART2 Error 40 32 IFS1<8> IEC1<8> IPC8<4:2> IPC8<1:0>

U2RX – UART2 Receiver 41 32 IFS1<9> IEC1<9> IPC8<4:2> IPC8<1:0>

U2TX – UART2 Transmitter 42 32 IFS1<10> IEC1<10> IPC8<4:2> IPC8<1:0>

I2C2B – I2C2 Bus Collision Event 43 33 IFS1<11> IEC1<11> IPC8<12:10> IPC8<9:8>

I2C2S – I2C2 Slave Event 44 33 IFS1<12> IEC1<12> IPC8<12:10> IPC8<9:8>

I2C2M – I2C2 Master Event 45 33 IFS1<13> IEC1<13> IPC8<12:10> IPC8<9:8>

FSCM – Fail-Safe Clock Monitor 46 34 IFS1<14> IEC1<14> IPC8<20:18> IPC8<17:16>

RTCC – Real-Time Clock and

Calendar

47 35 IFS1<15> IEC1<15> IPC8<28:26> IPC8<25:24>

DMA0 – DMA Channel 0 48 36 IFS1<16> IEC1<16> IPC9<4:2> IPC9<1:0>

DMA1 – DMA Channel 1 49 37 IFS1<17> IEC1<17> IPC9<12:10> IPC9<9:8>

DMA2 – DMA Channel 2 50 38 IFS1<18> IEC1<18> IPC9<20:18> IPC9<17:16>

DMA3 – DMA Channel 3 51 39 IFS1<19> IEC1<19> IPC9<28:26> IPC9<25:24>

FCE – Flash Control Event 56 44 IFS1<24> IEC1<24> IPC11<4:2> IPC11<1:0>

USB 57 45 IFS1<25> IEC1<25> IPC11<12:10> IPC11<9:8>

Lowest Natural Order Priority

TABLE 7-1: INTERRUPT IRQ AND VECTOR LOCATION (CONTINUED)

Interrupt Source

(1)

IRQ

Vector

Number

Interrupt Bit Location

Highest Natural Order Priority Flag Enable Priority Subpriority

Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MX General Purpose –

Features” and TABLE 2: “PIC32MX USB – Features” for available peripherals.