Datasheet

PIC32MX3XX/4XX DS61143H-page 68 © 2011 Microchip Technology Inc.
TABLE 4-17: COMPARATOR REGISTERS MAP
(1)
Virtual Address
(BF80_#)
Register
Name
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
A000 CM1CON
31:16
— — — — — — — — — — — — — — — — 0000
15:0 ON COE CPOL
— — — — COUT EVPOL<1:0> — CREF — — CCH<1:0> 00C3
A010 CM2CON
31:16
— — — — — — — — — — — — — — — — 0000
15:0 ON COE CPOL
— — — — COUT EVPOL<1:0> — CREF — — CCH<1:0> 00C3
A060 CMSTAT
31:16
— — — — — — — — — — — — — — — — 0000
15:0
— —SIDL— — — — — — — — — — — C2OUT C1OUT 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
TABLE 4-18: COMPARATOR VOLTAGE REFERENCE REGISTERS MAP
(1)
Virtual Address
(BF80_#)
Register
Name
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
9800 CVRCON
31:16
— — — — — — — — — — — — — — — — 0000
15:0 ON
— — — — — — — — CVROE CVRR CVRSS CVR<3:0> 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.