Datasheet

© 2011 Microchip Technology Inc. DS61143H-page 29
PIC32MX3XX/4XX
PGED2 18 27 J3 I/O ST Data I/O pin for programming/debugging
communication channel 2.
PGEC2 17 26 L1 I ST Clock input pin for programming/debugging
communication channel 2.
MCLR 7 13 F1 I/P ST Master Clear (Reset) input. This pin is an active-low
Reset to the device.
AV
DD 19 30 J4 P P Positive supply for analog modules. This pin must be
connected at all times.
AV
SS 20 31 L3 P P Ground reference for analog modules.
V
DD 10, 26, 38 2, 16, 37,
46, 62
C2, C9,
E5, F8,
G5, H4,
H6, K8
P — Positive supply for peripheral logic and I/O pins.
VCORE/
VCAP
56 85 B7 P — Capacitor for Internal Voltage Regulator.
Vss 9, 25, 41 15, 36,
45, 65,
75
A8, B10,
D4, D5,
E7, F10,
F5, G6,
G7, H3
P — Ground reference for logic and I/O pins.
V
REF+ 16 29 K3 I Analog Analog voltage reference (high) input.
V
REF- 15 28 L2 I Analog Analog voltage reference (low) input.
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
(1)
Pin
Type
Buffer
Type
Description
64-pin
QFN/TQFP
100-pin
TQFP
121-pin
XBGA
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.