Datasheet

PIC32MX3XX/4XX
DS61143H-page 28 © 2011 Microchip Technology Inc.
PMD0 60 93 A4 I/O TTL/ST Parallel Master Port Data (De-multiplexed Master
mode) or Address/Data (Multiplexed Master modes).
PMD1 61 94 B4 I/O TTL/ST
PMD2 62 98 B3 I/O TTL/ST
PMD3 63 99 A2 I/O TTL/ST
PMD4 64 100 A1 I/O TTL/ST
PMD5 1 3 D3 I/O TTL/ST
PMD6 2 4 C1 I/O TTL/ST
PMD7 3 5 D2 I/O TTL/ST
PMD8 — 90 A5 I/O TTL/ST
PMD9 — 89 E6 I/O TTL/ST
PMD10 — 88 A6 I/O TTL/ST
PMD11 — 87 B6 I/O TTL/ST
PMD12 — 79 A9 I/O TTL/ST
PMD13 — 80 D8 I/O TTL/ST
PMD14 — 83 D7 I/O TTL/ST
PMD15 — 84 C7 I/O TTL/ST
PMRD 53 82 B8 O — Parallel Master Port Read Strobe.
PMWR 52 81 C8 O — Parallel Master Port Write Strobe.
PMALL 30 44 L8 O — Parallel Master Port Address Latch Enable low-byte
(Multiplexed Master modes).
PMALH 29 43 K7 O — Parallel Master Port Address Latch Enable high-byte
(Multiplexed Master modes).
V
BUS 34 54 H8 I Analog USB Bus Power Monitor.
V
USB 35 55 H9 P — USB Internal Transceiver Supply. If the USB module
is not used, this pin must be connected to V
DD.
V
BUSON 11 20 H1 O — USB Host and OTG Bus Power Control Output.
D+ 37 57 H10 I/O Analog USB D+.
D- 36 56 J11 I/O Analog USB D-.
USBID 33 51 K10 I ST USB OTG ID Detect.
ENVREG 57 86 A7 I ST Enable for On-Chip Voltage Regulator.
TRCLK — 91 C5 O — Trace Clock.
TRD0 — 97 A3 O — Trace Data Bits 0-3.
TRD1 — 96 C3 O —
TRD2 — 95 C4 O —
TRD3 — 92 B5 O —
PGED1 16 25 K2 I/O ST Data I/O pin for programming/debugging
communication channel 1.
PGEC1 15 24 K1 I ST Clock input pin for programming/debugging
communication channel 1.
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
(1)
Pin
Type
Buffer
Type
Description
64-pin
QFN/TQFP
100-pin
TQFP
121-pin
XBGA
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.