Datasheet

© 2011 Microchip Technology Inc. DS61143H-page 165
PIC32MX3XX/4XX
FIGURE 29-4: POWER-ON RESET TIMING CHARACTERISTICS
VDD
VPOR
Note 1: The Power-up period will be extended if the power-up sequence completes before the device
exits from BOR (V
DD < VDDMIN).
2: Includes interval voltage regulator stabilization delay.
3: Power-up Timer (PWRT); only active when the internal voltage regulator is disabled.
SY00
Power Up Sequence
(Note 2)
VDD
VPOR
VCORE
External VCORE Provided
Internal Voltage Regulator Enabled
(TPU)
SY10
SY01
Power Up Sequence
(Note 3)
CPU starts fetching code
CPU starts fetching code
(TPWRT)
Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC)
VDD
VPOR
SY00
Power Up Sequence
(Note 2)
Internal Voltage Regulator Enabled
(TPU)
(T
SYSDLY)
CPU starts fetching code
(Note 1)
(Note 1)
(Note 1)
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
(TOST)
SY02
(T
SYSDLY)
SY02
(T
SYSDLY)
SY02