Datasheet

PIC32MX3XX/4XX
DS61143H-page 144 © 2011 Microchip Technology Inc.
RDPGPR Read GPR from Previous Shadow Set Rt = SGPR[SRSCtl
PSS
, Rd]
ROTR Rotate Word Right Rd = Rt
sa-1..0
|| Rt
31..sa
ROTRV Rotate Word Right Variable Rd = Rt
Rs-1..0
|| Rt
31..Rs
SB Store Byte (byte)Mem[Rs+offset] = Rt
SC Store Conditional Word if LL
bit
= 1
mem[Rs+offset> = Rt
Rt = LL
bit
SDBBP Software Debug Break Point Trap to SW Debug Handler
SEB Sign-Extend Byte Rd = SignExtend (Rs-7...0)
SEH Sign-Extend Half Rd = SignExtend (Rs-15...0)
SH Store Half (half)Mem[Rs+offset> = Rt
SLL Shift Left Logical Rd = Rt << sa
SLLV Shift Left Logical Variable Rd = Rt << Rs[4:0]
SLT Set on Less Than if (int)Rs < (int)Rt
Rd = 1
else
Rd = 0
SLTI Set on Less Than Immediate if (int)Rs < (int)Immed
Rt = 1
else
Rt = 0
SLTIU Set on Less Than Immediate Unsigned if (uns)Rs < (uns)Immed
Rt = 1
else
Rt = 0
SLTU Set on Less Than Unsigned if (uns)Rs < (uns)Immed
Rd = 1
else
Rd = 0
SRA Shift Right Arithmetic Rd = (int)Rt >> sa
SRAV Shift Right Arithmetic Variable Rd = (int)Rt >> Rs[4:0]
SRL Shift Right Logical Rd = (uns)Rt >> sa
SRLV Shift Right Logical Variable Rd = (uns)Rt >> Rs[4:0]
SSNOP Superscalar Inhibit No Operation NOP
SUB Integer Subtract Rt = (int)Rs - (int)Rd
SUBU Unsigned Subtract Rt = (uns)Rs - (uns)Rd
SW Store Word Mem[Rs+offset] = Rt
SWL Store Word Left Mem[Rs+offset] = Rt
SWR Store Word Right Mem[Rs+offset] = Rt
SYNC Synchronize Orders the cached coherent and
uncached loads and stores for access to
the shared memory
SYSCALL System Call SystemCallException
TEQ Trap if Equal if Rs == Rt
TrapException
TEQI Trap if Equal Immediate if Rs == (int)Immed
TrapException
TABLE 27-1: MIPS32
®
INSTRUCTION SET (CONTINUED)
Instruction Description Function
Note 1: This instruction is deprecated and should not be used.