Datasheet

© 2011 Microchip Technology Inc. DS61143H-page 143
PIC32MX3XX/4XX
JAL Jump and Link GPR[31] = PC + 8
PC = PC[31:28] || offset<<2
JALR Jump and Link Register Rd = PC + 8
PC = Rs
JALR.HB Jump and Link Register with Hazard Barrier Like JALR, but also clears execution and
instruction hazards
JR Jump Register PC = Rs
JR.HB Jump Register with Hazard Barrier Like JR, but also clears execution and
instruction hazards
LB Load Byte Rt = (byte)Mem[Rs+offset]
LBU Unsigned Load Byte Rt = (ubyte))Mem[Rs+offset]
LH Load Halfword Rt = (half)Mem[Rs+offset]
LHU Unsigned Load Halfword Rt = (uhalf)Mem[Rs+offset]
LL Load Linked Word Rt = Mem[Rs+offset>
LL
bit
= 1
LLAdr = Rs + offset
LUI Load Upper Immediate Rt = immediate << 16
LW Load Word Rt = Mem[Rs+offset]
LWPC Load Word, PC relative Rt = Mem[PC+offset]
LWL Load Word Left Re = Re MERGE Mem[Rs+offset]
LWR Load Word Right Re = Re MERGE Mem[Rs+offset]
MADD Multiply-Add HI | LO += (int)Rs * (int)Rt
MADDU Multiply-Add Unsigned HI | LO += (uns)Rs * (uns)Rt
MFC0 Move from Coprocessor 0 Rt = CPR[0, Rd, sel]
MFHI Move from HI Rd = HI
MFLO Move from LO Rd = LO
MOVN Move Conditional on Not Zero if Rt ¼ 0 then
Rd = Rs
MOVZ Move Conditional on Zero if Rt = 0 then
Rd = Rs
MSUB Multiply-Subtract HI | LO -= (int)Rs * (int)Rt
MSUBU Multiply-Subtract Unsigned HI | LO -= (uns)Rs * (uns)Rt
MTC0 Move to Coprocessor 0 CPR[0, n, Sel] = Rt
MTHI Move to HI HI = Rs
MTLO Move to LO LO = Rs
MUL Multiply with register write HI | LO =Unpredictable
Rd = ((int)Rs * (int)Rt)
31..0
MULT Integer Multiply HI | LO = (int)Rs * (int)Rd
MULTU Unsigned Multiply HI | LO = (uns)Rs * (uns)Rd
NOP No Operation
(Assembler idiom for: SLL r0, r0, r0)
NOR Logical NOR Rd = ~(Rs | Rt)
OR Logical OR Rd = Rs | Rt
ORI Logical OR Immediate Rt = Rs | Immed
RDHWR Read Hardware Register (if enabled by HWRE
na
Register)
Re = HWR[Rd]
TABLE 27-1: MIPS32
®
INSTRUCTION SET (CONTINUED)
Instruction Description Function
Note 1: This instruction is deprecated and should not be used.