Datasheet

© 2011 Microchip Technology Inc. DS61143H-page 113
PIC32MX3XX/4XX
18.0 INTER-INTEGRATED
CIRCUIT™ (I
2
C™)
The I
2
C module provides complete hardware support
for both Slave and Multi-Master modes of the I
2
C serial
communication standard. Figure 18-1 illustrates the I
2
C
module block diagram.
The PIC32MX3XX/4XX devices have up to two I
2
C
interface modules, denoted as I2C1 and I2C2. Each
I
2
C module has a 2-pin interface: the SCLx pin is clock
and the SDAx pin is data.
Each I
2
C module, ‘I2Cx’ (x = 1 or 2), offers the following
key features:
•I
2
C Interface Supporting both Master and Slave
Operation.
•I
2
C Slave Mode Supports 7 and 10-bit Address.
•I
2
C Master Mode Supports 7 and 10-bit Address.
•I
2
C Port allows Bidirectional Transfers between
Master and Slaves.
• Serial Clock Synchronization for I
2
C Port can be
used as a Handshake Mechanism to Suspend
and Resume Serial Transfer (SCLREL control).
•I
2
C Supports Multi-master Operation; Detects Bus
Collision and Arbitrates Accordingly.
• Provides Support for Address Bit Masking.
Note 1: This data sheet summarizes the features
of the PIC32MX3XX/4XX family of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to Section 24. “Inter-Integrated
Circuit (I
2
C™)” (DS61116) of the “PIC32
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.