PIC32MX3XX/4XX Data Sheet High-Performance, General Purpose and USB, 32-bit Flash Microcontrollers © 2011 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC32MX3XX/4XX High-Performance, General Purpose and USB 32-bit Flash Microcontrollers High-Performance 32-bit RISC CPU: • MIPS32® M4K® 32-bit core with 5-stage pipeline • 80 MHz maximum frequency • 1.56 DMIPS/MHz (Dhrystone 2.
PIC32MX3XX/4XX TABLE 1: PIC32MX GENERAL PURPOSE – FEATURES (1) EUART/SPI/I2C™ 10-bit ADC (ch) Comparators PMP/PSP JTAG 8 5/5/5 0 Yes No 2/2/2 16 2 Yes Yes Trace 32 + 12(1) VREG 40 Programmable DMA Channels PT, MR Timers/Capture/Compare Program Memory (KB) 64 Data Memory (KB) MHz PIC32MX320F032H Packages(2) Device Pins GENERAL PURPOSE PIC32MX320F064H 64 PT, MR 80 64 + 12 16 5/5/5 0 Yes No 2/2/2 16 2 Yes Yes PIC32MX320F128H 64 PT, MR 80 128 + 12(1) 16 5/5/5
PIC32MX3XX/4XX TABLE 2: PIC32MX USB – FEATURES Timers/Capture/Compare Programmable DMA Channels Dedicated USB DMA Channels VREG Trace EUART/SPI/I2C™ 10-bit ADC (ch) Comparators PMP/PSP JTAG 0 2 Yes No 2/1/2 16 2 Yes Yes 80 128 + 12 32 5/5/5 4 2 Yes No 2/1/2 16 2 Yes Yes 80 256 + 12(1) 32 5/5/5 4 2 Yes No 2/1/2 16 2 Yes Yes 80 512 + 12(1) 32 5/5/5 4 2 Yes No 2/1/2 16 2 Yes Yes 80 128 + 12(1) 32 5/5/5 4 2 Yes No 2/2/2 16 2 Yes Yes 80 2
PIC32MX3XX/4XX Pin Diagrams = Pins are up to 5V tolerant PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 RF1 RF0 ENVREG VCAP/VCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 64-Pin QFN (General Purpose) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PMD5/RE5 PMD6/RE6 PMD7/RE7 SCK2/PMA5/CN8/RG6 SDI2/PMA4/CN9/RG7 SDO2/PMA3/CN10/RG8 MCLR SS2/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/SS1/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1
PIC32MX3XX/4XX Pin Diagrams (Continued) 64-Pin TQFP (General Purpose) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 RF1 RF0 ENVREG VCAP/VCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 = Pins are up to 5V tolerant PMD5/RE5 PMD6/RE6 PMD7/RE7 SCK2/PMA5/CN8/RG6 SDI2/PMA4/CN9/RG7 SDO2/PMA3/CN10/RG8 MCLR SS2/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/SS1/CN4/RB2 PIC32MX320F032H PIC32
PIC32MX3XX/4XX Pin Diagrams (Continued) = Pins are up to 5V tolerant 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PMD4/RE4 PMD3/RE3 PMD2/RE2 TRD0/RG13 TRD1/RG12 TRD2/RG14 PMD1/RE1 PMD0/RE0 TRD3/RA7 TRCLK/RA6 PMD8/RG0 PMD9/RG1 PMD10/RF1 PMD11/RF0 ENVREG VCAP/VCORE PMD15/CN16/RD7 PMD14/CN15/RD6 PMRD/CN14/RD5 OC5/PMWR/CN13/RD4 PMD13/CN19/RD13 IC5/PMD12/RD12 OC4/RD3 OC3/RD2 OC2/RD1 100-Pin TQFP (General Purpose) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 2
PIC32MX3XX/4XX Pin Diagrams (Continued) 121-Pin XBGA(1) = Pins are up to 5V tolerant PIC32MX320F128L PIC32MX340F128L PIC32MX360F256L PIC32MX360F512L 1 2 3 4 5 6 7 8 9 10 11 RE4 RE3 RG13 RE0 RG0 RF1 ENVREG VSS RD12 RD2 RD1 NC RG15 RE2 RE1 RA7 RF0 VCORE/ VCAP RD5 RD3 VSS RC14 RE6 VDD RG12 RG14 RA6 NC RD7 RD4 VDD RC13 RD11 RC1 RE7 RE5 VSS VSS NC RD6 RD13 RD0 NC RD10 RC4 RC3 RG6 RC2 VDD RG1 VSS RA15 RD8 RD9 RA14 MCLR RG8 RG9 RG7 VSS NC NC
PIC32MX3XX/4XX TABLE 3: PIN NAMES: PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F128L, AND PIC32MX360F512L DEVICES Pin Number Full Pin Name Pin Number Full Pin Name A1 PMD4/RE4 E8 INT4/RA15 A2 PMD3/RE3 E9 RTCC/IC1/RD8 A3 TRD0/RG13 E10 IC2/RD9 A4 PMD0/RE0 E11 INT3/RA14 A5 PMD8/RG0 F1 MCLR A6 PMD10/RF1 F2 SDO2/PMA3/CN10/RG8 A7 ENVREG F3 SS2/PMA2/CN11/RG9 A8 VSS F4 SDI2/PMA4/CN9/RG7 A9 IC5/PMD12/RD12 F5 VSS A10 OC3/RD2 F6 No Connect (NC) A11 OC2/RD1 F7 No Connect
PIC32MX3XX/4XX TABLE 3: PIN NAMES: PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F128L, AND PIC32MX360F512L DEVICES (CONTINUED) Pin Number Full Pin Name Pin Number Full Pin Name K4 AN8/C1OUT/RB8 L3 AVSS K5 No Connect (NC) L4 AN9/C2OUT/RB9 K6 U2CTS/RF12 L5 AN10/CVREFOUT/PMA13/RB10 K7 AN14/PMALH/PMA1/RB14 L6 U2RTS/RF13 K8 VDD L7 AN13/PMA10/RB13 K9 U1RTS/CN21/RD15 L8 AN15/OCFB/PMALL/PMA0/CN12/RB15 K10 U1TX/RF3 L9 CN20/U1CTS/RD14 K11 U1RX/RF2 L10 U2RX/PMA9/CN17/RF4 L1 PGEC2/
PIC32MX3XX/4XX Pin Diagrams (Continued) 64-Pin QFN (USB) PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 RF1 RF0 ENVREG VCAP/VCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 U1TX/OC4/RD3 U1RX/OC3/RD2 U1RTS/OC2/RD1 = Pins are up to 5V tolerant 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PMD5/RE5 PMD6/RE6 PMD7/RE7 SCK2/PMA5/CN8/RG6 SDI2/PMA4/CN9/RG7 SDO2/PMA3/CN10/RG8 MCLR SS2/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/C
PIC32MX3XX/4XX Pin Diagrams (Continued) 64-Pin TQFP (USB) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 RF1 RF0 ENVREG VCAP/VCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 U1TX/OC4/RD3 U1RX/OC3/RD2 U1RTS/OC2/RD1 = Pins are up to 5V tolerant PMD5/RE5 PMD6/RE6 PMD7/RE7 SCK2/PMA5/CN8/RG6 SDI2/PMA4/CN9/RG7 SDO2/PMA3/CN10/RG8 MCLR SS2/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-
PIC32MX3XX/4XX Pin Diagrams (Continued) 100-Pin TQFP (USB) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PIC32MX440F128L PIC32MX460F256L PIC32MX460F512L 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VSS SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 SDO1/OC1/INT0/RD0 IC4/PMCS1/PMA14/RD11 SCK1/IC3/PMCS2/PMA15/RD10 SS1/IC2/RD9 RTCC/IC1/RD8 SDA1/INT4/RA15 SCL1/INT3/RA14 VSS OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 D+/RG2 D-/RG3 VUSB VBUS U1TX
PIC32MX3XX/4XX Pin Diagrams (Continued) 121-Pin XBGA(1) = Pins are up to 5V tolerant PIC32MX440F128L PIC32MX460F256L PIC32MX460F512L 1 2 3 4 5 6 7 8 9 10 11 RE4 RE3 RG13 RE0 RG0 RF1 ENVREG VSS RD12 RD2 RD1 NC RG15 RE2 RE1 RA7 RF0 VCORE/ VCAP RD5 RD3 VSS RC14 RE6 VDD RG12 RG14 RA6 NC RD7 RD4 VDD RC13 RD11 RC1 RE7 RE5 VSS VSS NC RD6 RD13 RD0 NC RD10 RC4 RC3 RG6 RC2 VDD RG1 VSS RA15 RD8 RD9 RA14 MCLR RG8 RG9 RG7 VSS NC NC VDD RC12 VSS
PIC32MX3XX/4XX TABLE 4: PIN NAMES: PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES Pin Number Full Pin Name Pin Number Full Pin Name A1 PMD4/RE4 E8 SDA1/INT4/RA15 A2 PMD3/RE3 E9 RTCC/IC1/RD8 A3 TRD0/RG13 E10 SS1/IC2/RD9 A4 PMD0/RE0 E11 SCL1/INT3/RA14 A5 PMD8/RG0 F1 MCLR A6 PMD10/RF1 F2 SDO2/PMA3/CN10/RG8 A7 ENVREG F3 SS2/PMA2/CN11/RG9 A8 VSS F4 SDI2/PMA4/CN9/RG7 A9 IC5/PMD12/RD12 F5 VSS A10 OC3/RD2 F6 No Connect (NC) A11 OC2/RD1 F7 No Connect (NC
PIC32MX3XX/4XX TABLE 4: PIN NAMES: PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES (CONTINUED) Pin Number Full Pin Name Pin Number Full Pin Name K4 AN8/C1OUT/RB8 L3 AVSS K5 No Connect (NC) L4 AN9/C2OUT/RB9 K6 U2CTS/RF12 L5 AN10/CVREFOUT/PMA13/RB10 K7 AN14/PMALH/PMA1/RB14 L6 U2RTS/RF13 K8 VDD L7 AN13/PMA10/RB13 K9 U1RTS/CN21/RD15 L8 AN15/OCFB/PMALL/PMA0/CN12/RB15 K10 USBID/RF3 L9 U1CTS/CN20/RD14 K11 U1RX/RF2 L10 U2RX/PMA9/CN17/RF4 L1 PGEC2/AN6/OCFA/RB6 L11
PIC32MX3XX/4XX Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 21 2.0 Guidelines for Getting Started with 32-bit Microcontrollers ........................................................................................................ 31 3.0 CPU............................................................................................................
PIC32MX3XX/4XX TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.
PIC32MX3XX/4XX NOTES: DS61143H-page 20 © 2011 Microchip Technology Inc.
PIC32MX3XX/4XX 1.0 DEVICE OVERVIEW This document contains device-specific information for the PIC32MX3XX/4XX devices. Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX3XX/4XX TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Number(1) Pin Name 64-pin 100-pin QFN/TQFP TQFP 121-pin XBGA Pin Type Buffer Type AN0 16 25 K2 I Analog AN1 15 24 K1 I Analog AN2 14 23 J2 I Analog AN3 13 22 J1 I Analog AN4 12 21 H2 I Analog AN5 11 20 H1 I Analog AN6 17 26 L1 I Analog AN7 18 27 J3 I Analog AN8 21 32 K4 I Analog AN9 22 33 L4 I Analog AN10 23 34 L5 I Analog AN11 24 35 J5 I Analog AN12 27 41 J7 I Analog AN
PIC32MX3XX/4XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name 64-pin 100-pin QFN/TQFP TQFP 121-pin XBGA Pin Type Buffer Type CN0 48 74 B11 I ST CN1 47 73 C10 I ST CN2 16 25 K2 I ST CN3 15 24 K1 I ST CN4 14 23 J2 I ST CN5 13 22 J1 I ST CN6 12 21 H2 I ST CN7 11 20 H1 I ST CN8 4 10 E3 I ST CN9 5 11 F4 I ST CN10 6 12 F2 I ST CN11 8 14 F3 I ST CN12 30 44 L8 I ST CN13 52 81 C8 I ST CN14 53 82 B8 I
PIC32MX3XX/4XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name 64-pin 100-pin QFN/TQFP TQFP 121-pin XBGA Pin Type Buffer Type Description INT3 44 66 E11 I ST External interrupt 3. INT4 45 67 E8 I ST External interrupt 4. RA0 — 17 G3 I/O ST PORTA is a bidirectional I/O port.
PIC32MX3XX/4XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name 64-pin 100-pin QFN/TQFP TQFP 121-pin XBGA Pin Type Buffer Type RD0 46 72 D9 I/O ST RD1 49 76 A11 I/O ST RD2 50 77 A10 I/O ST RD3 51 78 B9 I/O ST RD4 52 81 C8 I/O ST RD5 53 82 B8 I/O ST RD6 54 83 D7 I/O ST RD7 55 84 C7 I/O ST RD8 42 68 E9 I/O ST RD9 43 69 E10 I/O ST RD10 44 70 D11 I/O ST RD11 45 71 C11 I/O ST RD12 — 79 A9 I/O ST RD13 — 80
PIC32MX3XX/4XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name 64-pin 100-pin QFN/TQFP TQFP 121-pin XBGA Pin Type Buffer Type RG0 — 90 A5 I/O ST RG1 — 89 E6 I/O ST RG6 4 10 E3 I/O ST RG7 5 11 F4 I/O ST RG8 6 12 F2 I/O ST Description PORTG is a bidirectional I/O port.
PIC32MX3XX/4XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name 64-pin 100-pin QFN/TQFP TQFP 121-pin XBGA Pin Type Buffer Type Description TMS 23 17 G3 I ST JTAG Test mode select pin. TCK 27 38 J6 I ST JTAG test clock input pin. TDI 28 60 G11 I ST JTAG test data input pin. TDO 24 61 G9 O — JTAG test data output pin. RTCC 42 68 E9 O — Real-Time Clock Alarm Output. CVREF- 15 28 L2 I Analog Comparator Voltage Reference (low).
PIC32MX3XX/4XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name 64-pin 100-pin QFN/TQFP TQFP 121-pin XBGA Pin Type Buffer Type PMD0 60 93 A4 I/O TTL/ST PMD1 61 94 B4 I/O TTL/ST PMD2 62 98 B3 I/O TTL/ST PMD3 63 99 A2 I/O TTL/ST PMD4 64 100 A1 I/O TTL/ST PMD5 1 3 D3 I/O TTL/ST PMD6 2 4 C1 I/O TTL/ST PMD7 3 5 D2 I/O TTL/ST PMD8 — 90 A5 I/O TTL/ST PMD9 — 89 E6 I/O TTL/ST Description Parallel Master Port Data (De-multiplexed
PIC32MX3XX/4XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name 64-pin 100-pin QFN/TQFP TQFP 121-pin XBGA Pin Type Buffer Type Description PGED2 18 27 J3 I/O ST Data I/O pin for programming/debugging communication channel 2. PGEC2 17 26 L1 I ST Clock input pin for programming/debugging communication channel 2. MCLR 7 13 F1 I/P ST Master Clear (Reset) input. This pin is an active-low Reset to the device.
PIC32MX3XX/4XX NOTES: DS61143H-page 30 © 2011 Microchip Technology Inc.
PIC32MX3XX/4XX 2.0 GUIDELINES FOR GETTING STARTED WITH 32-BIT MICROCONTROLLERS Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices.
PIC32MX3XX/4XX FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION VDD 0.1 µF Ceramic CBP R R1 MCLR VSS VCAP/VCORE VDD CEFC C PIC32MX VSS 10Ω 2.2.1 VDD 0.1 µF Ceramic CBP VSS VDD AVSS VDD AVDD 0.1 µF Ceramic CBP VSS 0.1 µF Ceramic CBP 0.1 µF Ceramic CBP BULK CAPACITORS The use of a bulk capacitor is recommended to improve power supply stability. Typical values range from 4.7 µF to 47 µF. This capacitor should be located as close to the device as possible. 2.3 2.3.
PIC32MX3XX/4XX 2.5 ICSP Pins The PGECx and PGEDx pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms.
PIC32MX3XX/4XX 2.9 Configuration of Analog and Digital Pins During ICSP Operations If MPLAB ICD 2, ICD 3 or REAL ICE is selected as a debugger, it automatically initializes all of the Analogto-Digital input pins (ANx) as “digital” pins by setting all bits in the ADPCFG register. 2.10 Unused I/Os Unused I/O pins should not be allowed to float as inputs. They can be configured as outputs and driven to a logic-low state.
PIC32MX3XX/4XX 2.11 Referenced Sources This device data sheet is based on the following individual chapters of the “PIC32 Family Reference Manual”. These documents should be considered as the general reference for the operation of a particular module or device feature. Note 1: To access the documents listed below, browse to the documentation section of the PIC32MX460F512L product page on the Microchip web site (www.microchip.com) or select a family reference manual section from the following list.
PIC32MX3XX/4XX NOTES: DS61143H-page 36 © 2011 Microchip Technology Inc.
PIC32MX3XX/4XX 3.0 CPU Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 2. “CPU” (DS61113) of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). Resources for the MIPS32® M4K® Processor Core are available at: www.mips.com/products/cores/ 32-64-bit-cores/mips32-m4k/.
PIC32MX3XX/4XX 3.2 Architecture Overview The MIPS32® M4K® Processor Core contains several logic blocks working together in parallel, providing an efficient high performance computing engine. The following blocks are included with the core: • Execution Unit • Multiply/Divide Unit (MDU) • System Control Coprocessor (CP0) • Fixed Mapping Translation (FMT) • Dual Internal Bus interfaces • Power Management • MIPS16e Support • Enhanced JTAG (EJTAG) Controller 3.2.
PIC32MX3XX/4XX MIPS® M4K® PROCESSOR CORE HIGH-PERFORMANCE INTEGER MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES TABLE 3-1: Opcode Operand Size (mul rt) (div rs) Latency Repeat Rate MULT/MULTU, MADD/MADDU, MSUB/MSUBU 16 bits 1 1 32 bits 2 2 MUL 16 bits 2 1 32 bits 3 2 DIV/DIVU 8 bits 12 11 16 bits 19 18 24 bits 26 25 33 32 32 bits The MIPS architecture defines that the result of a multiply or divide operation be placed in the HI and LO registers.
PIC32MX3XX/4XX TABLE 3-2: COPROCESSOR 0 REGISTERS (CONTINUED) Register Register Number Name Function 17-22 Reserved Reserved 23 Debug(2) Debug control and exception status 24 DEPC(2) Program counter at last debug exception 25-29 Reserved Reserved 30 ErrorEPC(1) Program counter at last error 31 DESAVE(2) Debug handler scratchpad register Note 1: 2: Registers used in exception processing. Registers used during debug.
PIC32MX3XX/4XX 3.3 Power Management The MIPS32® M4K® Processor Core offers a number of power management features, including low-power design, active power management and power-down modes of operation. The core is a static design that supports slowing or halting the clocks, which reduces system power consumption during idle periods. 3.3.1 INSTRUCTION-CONTROLLED POWER MANAGEMENT The mechanism for invoking power-down mode is through execution of the WAIT instruction.
PIC32MX3XX/4XX NOTES: DS61143H-page 42 © 2011 Microchip Technology Inc.
PIC32MX3XX/4XX 4.0 MEMORY ORGANIZATION Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 3. “Memory Organization” (DS61115) of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). PIC32MX3XX/4XX microcontrollers provide 4 GB of unified virtual memory address space.
PIC32MX3XX/4XX FIGURE 4-1: MEMORY MAP ON RESET FOR PIC32MX320F032H AND PIC32MX420F032H DEVICES(1) Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 Physical Memory Map 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD008000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD007FFF Program Flash(2) 0xBD000000 0xA0002000 Reserved 0xA0001FFF RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x9FC02FEF 0x1FC03000 Device Configuration
PIC32MX3XX/4XX FIGURE 4-2: MEMORY MAP ON RESET FOR PIC32MX320F064H DEVICE(1) Virtual Memory Map 0xFFFFFFFF Physical Memory Map 0xFFFFFFFF Reserved 0xBFC03000 0xBFC02FFF Device Configuration Registers 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 Reserved 0xBF900000 SFRs 0xBF800000 Reserved 0xBD010000 KSEG1 0xBF8FFFFF Reserved 0xBD00FFFF Program Flash(2) 0xBD000000 Reserved 0xA0004000 0xA0003FFF RAM(2) 0xA0000000 0x1FC03000 Device Configuration Registers Reserved 0x9FC03000 0x9FC02FFF Device
PIC32MX3XX/4XX FIGURE 4-3: MEMORY MAP ON RESET FOR PIC32MX320F128H AND PIC32MX320F128L DEVICES(1) Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 Physical Memory Map 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD020000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD01FFFF Program Flash(2) 0xBD000000 0xA0004000 Reserved 0xA0003FFF RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x9FC02FEF 0x1FC03000 Device Configuration
PIC32MX3XX/4XX FIGURE 4-4: MEMORY MAP ON RESET FOR PIC32MX340F128H, PIC32MX340F128L, PIC32MX440F128H AND PIC32MX440F128L DEVICES(1) Virtual Memory Map 0xFFFFFFFF Physical Memory Map 0xFFFFFFFF Reserved 0xBFC03000 0xBFC02FFF Device Configuration Registers 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 Reserved 0xBF900000 SFRs 0xBF800000 Reserved 0xBD020000 KSEG1 0xBF8FFFFF Reserved 0xBD01FFFF Program Flash(2) 0xBD000000 Reserved 0xA0008000 0xA0007FFF RAM(2) 0xA0000000 0x1FC03000 Device Configura
PIC32MX3XX/4XX FIGURE 4-5: MEMORY MAP ON RESET FOR PIC32MX340F256H, PIC32MX360F256L, PIC32MX440F256H AND PIC32MX460F256L DEVICES(1) Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 Physical Memory Map 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD040000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD03FFFF Program Flash(2) 0xBD000000 0xA0008000 Reserved 0xA0007FFF RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x9FC02FE
PIC32MX3XX/4XX FIGURE 4-6: MEMORY MAP ON RESET FOR PIC32MX340F512H, PIC32MX360F512L, PIC32MX440F512H AND PIC32MX460F512L DEVICES(1) Virtual Memory Map 0xFFFFFFFF Physical Memory Map 0xFFFFFFFF Reserved 0xBFC03000 0xBFC02FFF Device Configuration Registers 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 Reserved 0xBF900000 SFRs 0xBF800000 Reserved 0xBD080000 KSEG1 0xBF8FFFFF Reserved 0xBD07FFFF Program Flash(2) 0xBD000000 Reserved 0xA0008000 0xA0007FFF RAM(2) 0xA0000000 0x1FC03000 Device Configura
Virtual Address (BF88_#) Register Name Bit Range BUS MATRIX REGISTERS MAP BMX CON(1) 31:16 — — — — — BMXCHEDMA — — — — — 2000 15:0 — — — — — — — — — BMXWSDRM — — — BMX DKPBA(1) 31:16 — — — — — — — — — — — — — — — — BMX DUDBA(1) 31:16 — — — — — — — — — — — — — — 0000 BMX DUPBA(1) 31:16 — — — — — — — — — — — — — — 0000 BMX DRMSZ 31:16 BMX PUPBA(1) 31:16 BMX PFMSZ 31:16 BMX BOOTSZ 31:16 2010 2020 2030 2040 2050 206
INTCON 1010 INTSTAT(2) 1020 IPTMR 1030 IFS0 1040 IFS1 1060 IEC0 1070 IEC1 1090 IPC0 10A0 IPC1 10B0 IPC2 10C0 IPC3 IPC4 10E0 IPC5 10F0 IPC6 1100 IPC7 1110 IPC8 DS61143H-page 51 1120 IPC9 1140 IPC11 Legend: Note 1: 2: 30/14 29/13 28/12 27/11 26/10 31:16 — — 15:0 — — — — — — — MVEC — 31:16 — — — — — 15:0 — — — — — 25/9 24/8 23/7 22/6 21/5 — — — — — — — — — SS0 — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000 — — — — — —
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Bits Register Name Virtual Address (BF88_#) INTERRUPT REGISTERS MAP FOR PIC32MX340F128H, PIC32MX340F256H, PIC32MX340F512H, PIC32MX340F128L, PIC32MX360F256L AND PIC32MX360F512L DEVICES ONLY(1) 31:16 — — — — — — — — — — — — — — — SS0 0000 — — — MVEC — TPC<2:0> — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000 15:0 31:16 — — — — — — — — — — — — — — — — 0000 1010 INTSTAT(2) 15:0 — — — — —
INTERRUPT REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H AND PIC32MX320F128L DEVICES ONLY(1) INTCON 1010 INTSTAT(2) 1020 IPTMR 1030 IFS0 1040 IFS1 1060 IEC0 1070 IEC1 1090 IPC0 10A0 IPC1 10B0 IPC2 IPC3 10D0 IPC4 10E0 IPC5 10F0 IPC6 1100 IPC7 1110 IPC8 DS61143H-page 53 1140 IPC11 Legend: Note 1: 2: 30/14 29/13 28/12 27/11 26/10 31:16 — — 15:0 — — — — — — — MVEC — 31:16 — — — — — 15:0 — — — — — 25/9 24/8 23/7 22/6 21/5 —
INTCON 1010 INTSTAT(2) © 2011 Microchip Technology Inc.
INTCON 1010 INTSTAT(2) 1020 IPTMR 1030 IFS0 1040 IFS1 1060 IEC0 1070 IEC1 1090 IPC0 10A0 IPC1 10B0 IPC2 10C0 IPC3 IPC4 10E0 IPC5 10F0 IPC6 1100 IPC7 1110 IPC8 DS61143H-page 55 1140 IPC11 Legend: Note 1: 2: 30/14 29/13 28/12 27/11 26/10 31:16 — — 15:0 — — — — — — — MVEC — 31:16 — — — — — 15:0 — — — — — 25/9 24/8 23/7 22/6 21/5 — — — — — — — — — SS0 — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000 — — — — — — — — 0000
Virtual Address (BF80_#) Register Name 0600 T1CON 0610 TMR1 0620 0800 PR1 T2CON 0810 TMR2 0820 0A00 PR2 T3CON 0A10 TMR3 0A20 0C00 PR3 T4CON 0C10 TMR4 0C20 © 2011 Microchip Technology Inc.
Virtual Address (BF80_#) Register Name 2000 IC1CON(1) IC1BUF IC2CON(1) 2210 2400 IC2BUF IC3CON(1) 2410 2600 IC3BUF IC4CON(1) 2610 2800 IC4BUF IC5CON(1) 2810 30/14 29/13 28/12 27/11 26/10 31:16 — 15:0 ON 25/9 — — — — — — — SIDL — — — FEDGE 31:16 24/8 23/7 22/6 21/5 — — — — C32 ICTMR 19/3 18/2 — — — ICOV ICBNE 17/1 16/0 — — ICM<2:0> 0000 0000 xxxx IC1BUF<31:0> 15:0 xxxx 31:16 — — — — — — — — — 15:0 ON — SIDL — — — FEDGE C32 ICTMR
Virtual Address (BF80_#) 3000 OC1CON 3010 3020 OC1R OC1RS 3200 OC2CON 3210 3220 OC2R OC2RS 3400 OC3CON 3410 3420 OC3R OC3RS 3600 OC4CON 3610 3620 OC4R OC4RS © 2011 Microchip Technology Inc.
Virtual Address (BF80_#) Register Name 5000 I2C1CON 5010 5020 5030 5040 5050 5260 5200 5210 5230 5240 5250 5260 I2C1STAT I2C1ADD I2C1MSK I2C1BRG I2C1TRN I2C1RCV I2C2CON I2C2STAT I2C2ADD I2C2MSK I2C2BRG I2C2TRN I2C2RCV DS61143H-page 59 Legend: Note 1: 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 31/15 30/14 31:16 — — — — — — — — — — — — — — — — 15:0 ON — SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT AC
Virtual Address (BF80_#) 6020 U1STA(1) U1TXREG 6030 U1RXREG 6040 (1) U1BRG 6200 U2MODE(1) 6210 6220 6230 6240 U2STA (1) U2TXREG U2RXREG U2BRG(1) Legend: Note 1: 31/15 30/14 29/13 28/12 31:16 — — — — 15:0 ON — SIDL IREN 31:16 — — 15:0 UTXISEL<1:0> 31:16 — 27/11 26/10 25/9 24/8 — — — — RTSMD — UEN<1:0> — — — — — ADM_EN UTXINV URXEN UTXBRK UTXEN UTXBF TRMT — — — — — — — 15:0 — — — — — — — TX8 31:16 — — — — — — — — 15:0 — — — —
Virtual Address (BF80_#) Register Name 5800 SPI1CON 5810 SPI1STAT 5820 5830 SPI1BUF SPI1BRG 5A00 SPI2CON 5A10 SPI2STAT 5A20 SPI2BUF 5A30 SPI2BRG Legend: Note 1: 2: 31/15 30/14 29/13 FRMSYNC FRMPOL 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bits Bit Range © 2011 Microchip Technology Inc.
9010 AD1CON2(1) 9020 AD1CON3(1) 9040 AD1CHS(1) 9060 AD1PCFG(1) 9050 AD1CSSL(1) 9070 ADC1BUF0 9080 ADC1BUF1 9090 ADC1BUF2 90A0 ADC1BUF3 90B0 ADC1BUF4 90C0 ADC1BUF5 © 2011 Microchip Technology Inc.
9110 ADC1BUFA 9120 ADC1BUFB 9130 ADC1BUFC 9140 ADC1BUFD 9150 ADC1BUFE 9160 ADC1BUFF Legend: Note 1: ADC REGISTERS MAP (CONTINUED) 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 ADC Result Word A (ADC1BUFA<31:0>) All Resets Bit Range Bits Register Name Virtual Address (BF80_#) © 2011 Microchip Technology Inc.
Virtual Address (BF88_#) DMASTAT 3020 DMAADDR 30/14 31:16 — — 15:0 ON — 31:16 — — 15:0 — — 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — — — — — 0000 SIDL SUSPEND — — — — — — — — — — — — 0000 — — — — — — — — — — — — — — 0000 — — — — — — — — — — RDWR — DMACH<1:0> 0000 DMAADDR<31:0> 15:0 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Virtual Address (BF88_#) 3060 DCH0CON 3070 DCH0ECON 3080 3090 DCH0INT DCH0SSA 30A0 DCH0DSA 30B0 DCH0SSIZ 30C0 DCH0DSIZ 30D0 DCH0SPTR 30E0 DCH0DPTR 3100 DCH0CPTR DCH0DAT 3120 DCH1CON 3130 DCH1ECON DS61143H-page 65 3140 3150 DCH1INT 29/13 28/12 27/11 26/10 25/9 31:16 — — — — — — — — — — 15:0 — — — — — — — CHCHNS CHEN CHAED 31:16 — — — — — — — — CFORCE CABORT PATEN SIRQEN AIRQEN — — — 15:0 24/8 CHSIRQ<7:0> 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 —
Virtual Address (BF88_#) Register Name 3160 DCH1DSA 3180 DCH1DSIZ 3190 DCH1SPTR 31A0 DCH1DPTR 31B0 DCH1CSIZ 31C0 DCH1CPTR 31D0 DCH1DAT 31E0 DCH2CON 31F0 DCH2ECON 3210 © 2011 Microchip Technology Inc.
Virtual Address (BF88_#) 3260 DCH2DPTR 3270 DCH2CSIZ 3280 DCH2CPTR 3290 DCH2DAT 32A0 DCH3CON 32B0 DCH3ECON 32C0 DCH3INT 32D0 DCH3SSA 32E0 DCH3DSA 3300 DCH3DSIZ 3310 DCH3SPTR 3320 DCH3DPTR 3330 DCH3CSIZ DS61143H-page 67 3340 DCH3CPTR DCH3DAT Legend: Note 1: 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 31:16 — — — — — — — — — — — 15:0 — — — — — — — — 31:16 — — — — — — — — 15:0 — — — — — — — — 31:16 — — — — — — — — 20/4 19/3 18/2
Virtual Address (BF80_#) Register Name A000 CM1CON A060 CM2CON CMSTAT Legend: Note 1: 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 — 31:16 — — — — — — — — 15:0 ON COE CPOL — — — — COUT 31:16 — — — — — — — — 15:0 ON COE CPOL — — — — COUT 31:16 — — — — — — — — 20/4 19/3 18/2 17/1 16/0 — — — — — — — EVPOL<1:0> — CREF — — — — — — — — EVPOL<1:0> — CREF — — — — — — — — CCH<1:0> — — CCH<1:0> — — All Reset
Virtual Address (BF80_#) F440 NVMSRC ADDR Legend: Note 1: 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — 31:16 — — — — — — — — — — — — 15:0 WR WREN WRERR LVDERR LVDSTAT — — — — — — — NVMOP<3:0> 0000 0000 0000 NVMKEY<31:0> 0000 31:16 0000 NVMADDR<31:0> 15:0 0000 31:16 0000 NVMDATA<31:0> 15:0 0000 31:16 NVMSRCADDR<31:0> 15:0 x = unknown value on Reset, — = unimplemented, read as ‘0’.
Virtual Address (BF88_#) Register Name 6000 TRISA PORTA 6020 LATA 6030 ODCA Legend: Note 1: 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 — — — — — — — — — — — — — — — — 0000 15:0 TRISA15 TRISA14 — — — TRISA10 TRISA9 — TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 C6FF 31:16 — — — — — — — — — — — — — — — — 0000 15:0 RA15 RA14 — — — RA10 RA9 — RA7 RA6 RA5 RA4 RA3 RA2
Virtual Address (BF88_#) Register Name 6080 TRISC PORTC 60A0 LATC 60B0 ODCC Legend: Note 1: 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 — — — — — — — — — — — — — — — — 0000 15:0 TRISC15 TRISC14 TRISC13 TRISC12 — — — — — — — TRISC4 TRISC3 TRISC2 TRISC1 — F01E 31:16 — — — — — — — — — — — — — — — — 0000 15:0 RC15 RC14 RC13 RC12 — — — — — — — RC4 RC3 RC2 RC1 — xxxx 31:16 —
Virtual Address (BF88_#) Register Name 60C0 TRISD PORTD 60E0 LATD 60F0 ODCD Legend: Note 1: 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 — — — — — — — — — — — — — — — — 0000 15:0 TRISD15 TRISD14 TRISD13 TRISD12 TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 FFFF 31:16 — — — — — — — — — — — — — — — — 0000 15:0 RD15 RD14 RD13 RD12 RD11 RD10 RD9 R
Virtual Address (BF88_#) Register Name 6100 TRISE PORTE 6120 LATE 6130 ODCE Legend: Note 1: 31/15 30/14 29/13 28/12 27/11 26/10 31:16 — — — — — — — — — — — — — — — — 15:0 — — — — — — TRISE9 TRISE8 TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 03FF 31:16 — — — — — — — — — — — — — — — — 0000 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0000 15:0 — — — — — — RE9 RE8 RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx 31:
Virtual Address (BF88_#) Register Name 6140 TRISF PORTF 6160 LATF 6170 ODCF 31/15 30/14 28/12 27/11 26/10 25/9 31:16 — — 15:0 — — 31:16 — — 15:0 — — 31:16 — — 15:0 — — 31:16 — — — 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — — — — — 0000 TRISF13 TRISF12 — — — TRISF8 TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 31FF — — — — — — — — — — — — — — 0000 RF13 RF12 — — — RF8 RF7 RF6 RF5
Virtual Address (BF88_#) Register Name 6140 TRISF PORTF 6160 LATF 6170 ODCF 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 21/5 20/4 19/3 18/2 17/1 16/0 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 07FF 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — RF6 RF5 RF4 RF3 RF2 RF1 RF0 xxxx 31:16 — — — — — — — — — — — —
Virtual Address (BF88_#) Register Name 6180 TRISG PORTG 61A0 LATG 61B0 ODCG Legend: Note 1: 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 — — — — — — — — — — — — — — — — 15:0 TRISG15 TRISG14 TRISG13 TRISG12 — — TRISG9 TRISG8 TRISG7 TRISG6 — — TRISG3 TRISG2 TRISG1 TRISG0 F3CF 31:16 — — — — — — — — — — — — — — — — 0000 0000 15:0 RG15 RG14 RG13 RG12 — — RG9 RG8 RG7 RG6 — — RG3 RG2
Virtual Address (BF88_#) Register Name 61C0 CNCON CNEN CNPUE 31/15 30/14 31:16 — 15:0 ON 31:16 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — — — — — — 0000 — SIDL — — — — — — — — — — — — — 0000 — — — — — — — — — — CNEN21 CNEN20 CNEN19 CNEN18 CNEN17 CNEN16 0000 15:0 CNEN15 CNEN14 CNEN13 CNEN12 CNEN11 CNEN10 CNEN9 CNEN8 CNEN7 CNEN6 CNEN5 CNEN4 CNEN3 CNEN2 CNEN1 CNEN0 0000
Virtual Address (BF80_#) Register Name 7000 PMCON 7010 PMMODE 7020 PMADDR 7030 PMDOUT 7040 7060 PMAEN PMSTAT Legend: Note 1: 30/14 31:16 — — — 15:0 ON — SIDL 31:16 — — — 15:0 BUSY 31:16 — IRQM<1:0> — 28/12 27/11 — — ADRMUX<1:0> — — INCM<1:0> — — 26/10 24/8 23/7 22/6 — — — — — PMPTTL PTWREN PTRDEN — — — MODE16 — 25/9 — CSF<1:0> — MODE<1:0> — — 21/5 — — 20/4 19/3 18/2 17/1 16/0 — — — — — — ALP CS2P CS1P — WRSP RDSP 0000 — — — —
Virtual Address (BF88_#) 4010 CHEACC(1) 4020 CHETAG (1) 4030 CHEMSK(1) 4040 CHEW0 4050 CHEW1 4060 CHEW2 4070 CHEW3 CHELRU 4090 CHEMIS 40C0 CHEPFABT Legend: Note 1: 30/14 29/13 28/12 27/11 26/10 — — — — — — — — — — — — 31:16 CHEWEN — — — — — 31:16 LTAGBOOT — — — — — — — — — — — — — LMASK<15:5> 31:16 15:0 15:0 — 15:0 23/7 22/6 — — DCSZ<1:0> — — — — — — — — — — — — — — — — — — 31:16 31:16 31:16 31:16 31:16 15:0 31:16 18/2 — — PREFEN<1:0> — — — — —
Virtual Address (BF80_#) Register Name 0200 RTCCON 0220 0230 RTCALRM RTCTIME RTCDATE 0240 ALRMTIME 0250 ALRMDATE Legend: Note 1: 30/14 31:16 — 15:0 ON 28/12 27/11 26/10 — — — — — — SIDL — — — 31:16 — — — — 15:0 ALRMEN CHIME PIV ALRMSYNC 25/9 24/8 — — — — — — HR01<3:0> 15:0 SEC10<3:0> SEC01<3:0> 31:16 YEAR10<3:0> YEAR01<3:0> 15:0 DAY10<3:0> DAY01<3:0> 31:16 MIN10<3:0> MIN01<3:0> 15:0 SEC10<3:0> SEC01<3:0> — — — — 22/6 21/5 20/4 RTSECSEL RTCCLKO
Virtual Address (BF80_#) Register Name F220 DEVID Legend: DEVICE AND REVISION ID SUMMARY 31:16 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 VER<3:0> 15:0 DEVID<15:0> x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 22/6 21/5 DEVID<27:16> 20/4 19/3 18/2 17/1 16/0 All Resets Bits Bit Range © 2011 Microchip Technology Inc.
Virtual Address (BF88_#) Register Name Bit Range 5040 U1OTG IR(2) 31:16 — — — — — — — — — 15:0 — — — — — — — — IDIF 5050 U1OTG IE 31:16 — — — — — — — — — 15:0 — — — — — — — — IDIE 5060 U1OTG STAT(3) 31:16 — — — — — — — — — — — — — — — 15:0 — — — — — — — — ID — LSTATE — SESVD SESEND — 5070 U1OTG CON 31:16 — — — — — — — — — — — — — 15:0 — — — — — — — — 5080 U1PWRC 31:16 — — — — — — — — — — —
Virtual Address (BF88_#) 5280 U1FRML(3) 5290 U1FRMH(3) 52A0 52B0 U1TOK U1SOF 52C0 U1BDTP2 52D0 U1BDTP3 52E0 U1CNFG1 U1EP0 5310 U1EP1 5320 U1EP2 5330 U1EP3 5340 U1EP4 5350 U1EP5 5360 U1EP6 5370 U1EP7 DS61143H-page 83 Legend: Note 1: 2: 3: 4: All Resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 — — — — — — — — — — — — — — — — 15:0 — — — — — — — — 31:16 — — — — — — — — — — — — — 15:0
Virtual Address (BF88_#) Register Name 5380 U1EP8 5390 U1EP9 53A0 U1EP10 53B0 U1EP11 53C0 U1EP12 53D0 U1EP13 53E0 U1EP14 53F0 U1EP15 Legend: Note 1: 2: 3: 4: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 31:16 — — — — — — — — — — — — — — — 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL 31:16 — — — — — — — — — — — — — — — 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTX
PIC32MX3XX/4XX 5.0 FLASH PROGRAM MEMORY Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 5. “Flash Program Memory” (DS61121) of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices.
PIC32MX3XX/4XX NOTES: DS61143H-page 86 © 2011 Microchip Technology Inc.
PIC32MX3XX/4XX 6.0 RESETS Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 7. “Resets” (DS61118) of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.
PIC32MX3XX/4XX NOTES: DS61143H-page 88 © 2011 Microchip Technology Inc.
PIC32MX3XX/4XX 7.0 INTERRUPT CONTROLLER Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 8. “Interrupt Controller” (DS61108) of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices.
PIC32MX3XX/4XX TABLE 7-1: INTERRUPT IRQ AND VECTOR LOCATION Interrupt Source(1) IRQ Vector Number Highest Natural Order Priority Interrupt Bit Location Flag Enable Priority Subpriority CT – Core Timer Interrupt 0 0 IFS0<0> IEC0<0> IPC0<4:2> IPC0<1:0> CS0 – Core Software Interrupt 0 1 1 IFS0<1> IEC0<1> IPC0<12:10> IPC0<9:8> CS1 – Core Software Interrupt 1 2 2 IFS0<2> IEC0<2> IPC0<20:18> IPC0<17:16> INT0 – External Interrupt 0 3 3 IFS0<3> IEC0<3> IPC0<28:26> IPC0<25:24> T
PIC32MX3XX/4XX TABLE 7-1: INTERRUPT IRQ AND VECTOR LOCATION (CONTINUED) Interrupt Source(1) IRQ Vector Number Highest Natural Order Priority SPI2E – SPI2 Fault 37 31 Interrupt Bit Location Flag Enable Priority Subpriority IFS1<5> IEC1<5> IPC7<28:26> IPC7<25:24> SPI2TX – SPI2 Transfer Done 38 31 IFS1<6> IEC1<6> IPC7<28:26> IPC7<25:24> SPI2RX – SPI2 Receive Done 39 31 IFS1<7> IEC1<7> IPC7<28:26> IPC7<25:24> U2E – UART2 Error 40 32 IFS1<8> IEC1<8> IPC8<4:2> IPC8<1:0> U2RX –
PIC32MX3XX/4XX NOTES: DS61143H-page 92 © 2011 Microchip Technology Inc.
PIC32MX3XX/4XX 8.
PIC32MX3XX/4XX NOTES: DS61143H-page 94 © 2011 Microchip Technology Inc.
PIC32MX3XX/4XX 9.0 PREFETCH CACHE Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 4. “Prefetch Cache” (DS61119) of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices.
PIC32MX3XX/4XX NOTES: DS61143H-page 96 © 2011 Microchip Technology Inc.
PIC32MX3XX/4XX 10.0 DIRECT MEMORY ACCESS (DMA) CONTROLLER Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 31. “Direct Memory Access (DMA) Controller” (DS61117) of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX3XX/4XX NOTES: DS61143H-page 98 © 2011 Microchip Technology Inc.
PIC32MX3XX/4XX 11.0 USB ON-THE-GO (OTG) The PIC32MX USB module includes the following features: Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 27. “USB OnThe-Go (OTG)” (DS61126) of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX3XX/4XX FIGURE 11-1: PIC32MX3XX/4XX FAMILY USB INTERFACE DIAGRAM USBEN FRC Oscillator 8 MHz Typical USB Suspend CPU Clock Not POSC Sleep TUN<5:0>(4) Primary Oscillator (POSC) UFIN(5) PLL Div x Div 2 UFRCEN(3) OSC1 UPLLEN(6) UPLLIDIV(6) To Clock Generator for Core and Peripherals USB Suspend OSC2 (PB out)(1) Sleep or Idle USB Module SRP Charge VBUS SRP Discharge USB Voltage Comparators 48 MHz USB Clock(7) Full Speed Pull-up D+(2) Registers and Control Interface Host Pull-down SIE Tr
PIC32MX3XX/4XX 12.0 I/O PORTS General purpose I/O pins are the simplest of peripherals. They allow the PIC® MCU to monitor and control other devices. To add flexibility and functionality, some pins are multiplexed with alternate function(s). These functions depend on which peripheral features are on the device. In general, when a peripheral is functioning, that pin may not be used as a general purpose I/O pin. Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices.
PIC32MX3XX/4XX 12.1 Parallel I/O (PIO) Ports All port pins have three registers (TRIS, LAT and PORT) that are directly associated with their operation. TRIS is a data direction or tri-state control register that determines whether a digital pin is an input or an output. Setting a TRISx register bit = 1 configures the corresponding I/O pin as an input; setting a TRISx register bit = 0 configures the corresponding I/O pin as an output. All port I/O pins are defined as inputs after a device Reset.
PIC32MX3XX/4XX 13.0 TIMER1 This family of PIC32MX devices features one synchronous/asynchronous 16-bit timer that can operate as a free-running interval timer for various timing applications and counting external events. This timer can also be used with the Secondary Oscillator (SOSC) for real-time clock applications. The following modes are supported: Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source.
PIC32MX3XX/4XX NOTES: DS61143H-page 104 © 2011 Microchip Technology Inc.
PIC32MX3XX/4XX 14.0 TIMER2/3 AND TIMER4/5 Two 32-bit synchronous timers are available by combining Timer2 with Timer3 and Timer4 with Timer5. The 32-bit timers can operate in three modes: Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 14.
PIC32MX3XX/4XX FIGURE 14-2: TIMER2/3, 4/5 BLOCK DIAGRAM (32-BIT) Reset TMRy MSHalfWord ADC Event Trigger(3) Equal Sync LSHalfWord 32-bit Comparator PRy TyIF Event Flag TMRx PRx 0 1 TGATE (TxCON<7>) Q D TGATE (TxCON<7>) Q TCS (TxCON<1>) ON (TxCON<15>) TxCK(2) x1 Gate Sync PBCLK 10 00 Prescaler 1, 2, 4, 8, 16, 32, 64, 256 3 TCKPS (TxCON<6:4>) Note 1: In this diagram, the use of ‘x’ in registers TxCON, TMRx, PRx and TxCK refers to either Timer2 or Timer4; the use of ‘y’ in registers TyCON
PIC32MX3XX/4XX 15.0 INPUT CAPTURE 2. Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 15. “Input Capture” (DS61122) of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices.
PIC32MX3XX/4XX NOTES: DS61143H-page 108 © 2011 Microchip Technology Inc.
PIC32MX3XX/4XX 16.0 OUTPUT COMPARE The Output Compare module (OCMP) is used to generate a single pulse or a train of pulses in response to selected time base events. For all modes of operation, the OCMP module compares the values stored in the OCxR and/or the OCxRS registers to the value in the selected timer. When a match occurs, the OCMP module generates an event based on the selected mode of operation. Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices.
PIC32MX3XX/4XX NOTES: DS61143H-page 110 © 2011 Microchip Technology Inc.
PIC32MX3XX/4XX 17.0 SERIAL PERIPHERAL INTERFACE (SPI) The SPI module is a synchronous serial interface useful for communicating with external peripherals and other microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, Analog-to-Digital Converters, etc. The PIC32MX SPI module is compatible with Motorola® SPI and SIOP interfaces. Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices.
PIC32MX3XX/4XX NOTES: DS61143H-page 112 © 2011 Microchip Technology Inc.
PIC32MX3XX/4XX 18.0 INTER-INTEGRATED CIRCUIT™ (I2C™) Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 24. “Inter-Integrated Circuit (I2C™)” (DS61116) of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX3XX/4XX FIGURE 18-1: I2C™ BLOCK DIAGRAM (X = 1 OR 2) Internal Data Bus I2CxRCV Read SCLx Shift Clock I2CxRSR LSB SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation Control Logic I2CxSTAT Collision Detect Read Write I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSB Read Shift Clock Reload Control BRG Down Counter Write I2CxBRG Read PBCLK DS61143H-page 114 © 2011 Microchip Tech
PIC32MX3XX/4XX 19.0 Note UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 21. “Universal Asynchronous Receiver Transmitter (UART)” (DS61107) of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX3XX/4XX FIGURE 19-2: TRANSMISSION (8-BIT OR 9-BIT DATA) Write to UxTXREG BCLK/16 (Shift Clock) UxTX Character 1 Start bit bit 0 bit 1 Character 1 bit 7/8 Stop bit UxTXIF Cleared by User UxTXIF Character 1 to Transmit Shift Register TRMT bit FIGURE 19-3: TWO CONSECUTIVE TRANSMISSIONS Write to UxTXREG BCLK/16 (Shift Clock) UxTX UxTXIF (UTXISEL0 = 0) UxTXIF (UTXISEL0 = 1) Character 1 Character 2 Start bit bit 0 DS61143H-page 116 bit 7/8 Stop bit Start bit bit 0 Character 2 UxTXIF C
PIC32MX3XX/4XX FIGURE 19-4: UART RECEPTION UxRX Start bit bit 0 bit1 bit 7 Stop bit Start bit bit 0 bit 7 Stop bit UxRXIF (RXISEL = 0x) Character 2 to UxRXREG Character 1 to UxRXREG RIDLE bit Note: This timing diagram shows 2 characters received on the UxRX input.
PIC32MX3XX/4XX NOTES: DS61143H-page 118 © 2011 Microchip Technology Inc.
PIC32MX3XX/4XX 20.0 PARALLEL MASTER PORT (PMP) Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 13. “Parallel Master Port (PMP)” (DS61128) of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX3XX/4XX NOTES: DS61143H-page 120 © 2011 Microchip Technology Inc.
PIC32MX3XX/4XX 21.0 REAL-TIME CLOCK AND CALENDAR (RTCC) The following are some of the key features of this module: • • • • Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 29. “Real-Time Clock and Calendar (RTCC)” (DS61125) of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX3XX/4XX NOTES: DS61143H-page 122 © 2011 Microchip Technology Inc.
PIC32MX3XX/4XX 22.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. Refer to Section 17. “10-bit Analog-to-Digital Converter (ADC)” (DS61104) of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices.
PIC32MX3XX/4XX FIGURE 22-2: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM ADRC ADC Internal RC Clock(1) 1 TAD ADCS<7:0> 0 8 ADC Conversion Clock Multiplier TPB 2,4,..., 512 Note 1: See the ADC electrical characteristics for the exact RC clock value. DS61143H-page 124 © 2011 Microchip Technology Inc.
PIC32MX3XX/4XX 23.0 COMPARATOR Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. Refer to Section 19. “Comparator” (DS61110) of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.
PIC32MX3XX/4XX NOTES: DS61143H-page 126 © 2011 Microchip Technology Inc.
PIC32MX3XX/4XX 24.0 COMPARATOR VOLTAGE REFERENCE (CVREF) The CVREF is a 16-tap, resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it also may be used independently of them. Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. Refer to Section 20.
PIC32MX3XX/4XX NOTES: DS61143H-page 128 © 2011 Microchip Technology Inc.
PIC32MX3XX/4XX 25.0 POWER-SAVING FEATURES Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 10. “Power-Saving Features” (DS61130) of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices.
PIC32MX3XX/4XX The processor will exit, or ‘wake-up’, from Sleep on one of the following events: The processor will wake or exit from Idle mode on the following events: • On any interrupt from an enabled source that is operating in Sleep. The interrupt priority must be greater than the current CPU priority. • On any form of device Reset. • On a WDT time-out. See Section 26.2 “Watchdog Timer (WDT)”. • On any interrupt event for which the interrupt source is enabled.
PIC32MX3XX/4XX 26.0 SPECIAL FEATURES Note: This data sheet summarizes the features of the PIC32MX3XX/4XX family family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 9. “Watchdog Timer and Power-up Timer” (DS61114), Section 32. “Configuration” (DS61124) and Section 33. “Programming and Diagnostics” (DS61129) of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.
PIC32MX3XX/4XX REGISTER 26-1: DEVCFG0: DEVICE CONFIGURATION WORD 0 (CONTINUED) bit 19-12 PWP<7:0>: Program Flash Write-Protect bits Prevents selected program Flash memory pages from being modified during code execution. The PWP bits represent the one’s compliment of the number of write protected program Flash memory pages.
PIC32MX3XX/4XX REGISTER 26-2: Bit Range 31:24 23:16 15:8 7:0 DEVCFG1: DEVICE CONFIGURATION WORD 1 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 — — — — — — — — R/P r-1 r-1 R/P R/P R/P R/P R/P R/P r-1 R/P R/P R/P FWDTEN — — R/P R/P R/P FCKSM<1:0> WDTPS<4:0> — OSCIOFNC R/P r-1 R/P FPBDIV<1:0> r-1 r-1 R/P IESO — FSOSCEN — — POSCMOD<1:0> R/P R/P FNO
PIC32MX3XX/4XX REGISTER 26-2: DEVCFG1: DEVICE CONFIGURATION WORD 1 (CONTINUED) bit 13-12 FPBDIV<1:0>: Peripheral Bus Clock Divisor Default Value bits 11 = PBCLK is SYSCLK divided by 8 10 = PBCLK is SYSCLK divided by 4 01 = PBCLK is SYSCLK divided by 2 00 = PBCLK is SYSCLK divided by 1 bit 11 Reserved: Write ‘1’ bit 10 OSCIOFNC: CLKO Enable Configuration bit 1 = CLKO output signal active on the OSCO pin; primary oscillator must be disabled or configured for the External Clock mode (EC) for the CLKO to b
PIC32MX3XX/4XX REGISTER 26-3: Bit Range 31:24 23:16 15:8 7:0 DEVCFG2: DEVICE CONFIGURATION WORD 2 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 — — — — — — — — R/P R/P R/P r-1 r-1 r-1 r-1 r-1 — — — — — R/P r-1 r-1 r-1 r-1 UPLLEN — — — — r-1 R/P R/P R/P — Legend: R = Readable bit U = Unimplemented bit FPLLMUL<2:0> r-1 FPLLODIV<2:0> R/P R/P R/P UPL
PIC32MX3XX/4XX REGISTER 26-4: Bit Range 31:24 23:16 15:8 7:0 DEVCFG3: DEVICE CONFIGURATION WORD 3 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 — — — — — — — — r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 — — — — — — — — R/P R/P R/P R/P R/P R/P R/P R/P R/P R/P R/P R/P R/P R/P USERID<15:8> R/P R/P USERID<7:0> Legend: R = Readable bit W = Writable bit P = Prog
PIC32MX3XX/4XX 26.2 Watchdog Timer (WDT) This section describes the operation of the WDT and Power-Up Timer of the PIC32MX3XX/4XX. The WDT, when enabled, operates from the internal Low-Power Oscillator (LPRC) clock source and can be used to detect system software malfunctions by resetting the device if the WDT is not cleared periodically in software. Various WDT time-out periods can be selected using the WDT postscaler. The WDT can also be used to wake the device from Sleep or Idle mode.
PIC32MX3XX/4XX 26.3 On-Chip Voltage Regulator 26.3.1 ON-CHIP REGULATOR AND POR All PIC32MX3XX/4XX device’s core and digital logic are designed to operate at a nominal 1.8V. To simplify system designs, most devices in the PIC32MX3XX/4XX incorporate an on-chip regulator providing the required core logic voltage from VDD. When the voltage regulator is enabled, it takes fixed delay for it to generate output. During this time, designated as TPU, code execution is disabled.
PIC32MX3XX/4XX 26.4 Programming and Diagnostics PIC32MX3XX/4XX devices provide a complete range of programming and diagnostic features that can increase the flexibility of any application using them.
PIC32MX3XX/4XX REGISTER 26-6: Bit Range 31:24 23:16 15:8 7:0 DDPCON: DEBUG DATA PORT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 r-x r-x DDPUSB DDPU1 DDPU2 DDPSPI1 JTAGEN
PIC32MX3XX/4XX 27.0 INSTRUCTION SET The PIC32MX3XX/4XX family instruction set complies with the MIPS32 Release 2 instruction set architecture. PIC32MX does not support the following features: Table 27-1 provides a summary of the instructions that are implemented by the PIC32MX3XX/4XX family core.
PIC32MX3XX/4XX TABLE 27-1: MIPS32® INSTRUCTION SET (CONTINUED) Instruction Description Function (1) BLEZL Branch on Less Than or Equal to Zero Likely BLTZ Branch on Less Than Zero if Rs[31] PC += (int)offset BLTZAL Branch on Less Than Zero and Link GPR[31] = PC + 8 if Rs[31] PC += (int)offset BLTZALL Branch on Less Than Zero and Link Likely(1) GPR[31] = PC + 8 if Rs[31] PC += (int)offset else Ignore Next Instruction BLTZL Branch on Less Than Zero Likely(1) if Rs[31] PC += (int)offset else
PIC32MX3XX/4XX TABLE 27-1: MIPS32® INSTRUCTION SET (CONTINUED) Instruction Description Function JAL Jump and Link GPR[31] = PC + 8 PC = PC[31:28] || offset<<2 JALR Jump and Link Register Rd = PC + 8 PC = Rs JALR.HB Jump and Link Register with Hazard Barrier Like JALR, but also clears execution and instruction hazards JR Jump Register PC = Rs JR.
PIC32MX3XX/4XX TABLE 27-1: MIPS32® INSTRUCTION SET (CONTINUED) Instruction Description Function RDPGPR Read GPR from Previous Shadow Set Rt = SGPR[SRSCtlPSS, Rd] ROTR Rotate Word Right ROTRV Rotate Word Right Variable SB Store Byte Rd = Rtsa-1..0 || Rt31..sa Rd = RtRs-1..0 || Rt31..Rs (byte)Mem[Rs+offset] = Rt SC Store Conditional Word if LLbit = 1 mem[Rs+offset> = Rt Rt = LLbit SDBBP Software Debug Break Point Trap to SW Debug Handler SEB Sign-Extend Byte Rd = SignExtend (Rs-7...
PIC32MX3XX/4XX TABLE 27-1: MIPS32® INSTRUCTION SET (CONTINUED) Instruction Description Function TGE Trap if Greater Than or Equal if (int)Rs >= (int)Rt TrapException TGEI Trap if Greater Than or Equal Immediate if (int)Rs >= (int)Immed TrapException TGEIU Trap if Greater Than or Equal Immediate Unsigned if (uns)Rs >= (uns)Immed TrapException TGEU Trap if Greater Than or Equal Unsigned if (uns)Rs >= (uns)Rt TrapException TLT Trap if Less Than if (int)Rs < (int)Rt TrapException TLTI Trap
PIC32MX3XX/4XX NOTES: DS61143H-page 146 © 2011 Microchip Technology Inc.
PIC32MX3XX/4XX 28.
PIC32MX3XX/4XX 28.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 28.
PIC32MX3XX/4XX 28.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC32MX3XX/4XX 28.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 28.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC32MX3XX/4XX 29.0 ELECTRICAL CHARACTERISTICS This section provides an overview of PIC32MX3XX/4XX electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC32MX3XX/4XX are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability.
PIC32MX3XX/4XX 29.1 DC Characteristics TABLE 29-1: OPERATING MIPS VS. VOLTAGE Characteristic DC5 DC5b Note 1: Max. Frequency VDD Range (in Volts) Temp. Range (in °C) PIC32MX3XX/4XX 2.3V-3.6V -40°C to +85°C 80 MHz (Note 1) 2.3V-3.6V -40°C to +105°C 80 MHz (Note 1) 40 MHz maximum for PIC32MX320F032H and PIC32MX420F032H devices. TABLE 29-2: THERMAL OPERATING CONDITIONS Rating Symbol Min. Typical Max.
PIC32MX3XX/4XX TABLE 29-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp DC CHARACTERISTICS Param. No. Typical(3) Max. Units Conditions Operating Current (IDD)(1,2) DC20 8.5 13 9 15 mA Code executing from Flash — 4 MHz — — 20 MHz (Note 4) — — 60 MHz (Note 4) -40ºC, +25ºC, +85ºC 2.3V +105ºC DC20c 4.
PIC32MX3XX/4XX TABLE 29-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp DC CHARACTERISTICS Parameter No. Typical(2) Max. Units Conditions Idle Current (IIDLE): Core OFF, Clock ON Base Current (Note 1) DC30 — 5 mA -40ºC, +25ºC, +85ºC 2.3V DC30a 1.
PIC32MX3XX/4XX TABLE 29-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp DC CHARACTERISTICS Parameter Typical(2) No. Max.
PIC32MX3XX/4XX TABLE 29-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp DC CHARACTERISTICS Parameter Typical(2) No. Max.
PIC32MX3XX/4XX TABLE 29-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS DC CHARACTERISTICS Param. Symbol No. Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp Min. Typical(1) Max. Units with TTL Buffer VSS — 0.15 VDD V (Note 4) with Schmitt Trigger Buffer VSS — 0.2 VDD V (Note 4) MCLR VSS — 0.2 VDD V (Note 4) DI16 OSC1 (XT mode) VSS — 0.
PIC32MX3XX/4XX TABLE 29-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS DC CHARACTERISTICS Param. Symbol No. VOL DO10 Characteristics OSC2/CLKO VOH DO20 Typical Max. Units Conditions — — 0.4 V IOL = 7 mA, VDD = 3.6V — — 0.4 V IOL = 6 mA, VDD = 2.3V — — 0.4 V IOL = 3.5 mA, VDD = 3.6V — — 0.4 V IOL = 2.5 mA, VDD = 2.3V 2.4 — — V IOH = -12 mA, VDD = 3.6V 1.4 — — V IOH = -12 mA, VDD = 2.3V 2.4 — — V IOH = -12 mA, VDD = 3.6V 1.4 — — V IOH = -12 mA, VDD = 2.
PIC32MX3XX/4XX TABLE 29-11: DC CHARACTERISTICS: PROGRAM MEMORY(3) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp DC CHARACTERISTICS Param. No. Symbol Characteristics Min. Typical(1) Max. Units Conditions Program Flash Memory D130 EP Cell Endurance 1000 — — E/W — D131 VPR VDD for Read VMIN — 3.6 V — D132 VPEW VDD for Erase or Write 3.0 — 3.
PIC32MX3XX/4XX TABLE 29-13: COMPARATOR SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp DC CHARACTERISTICS Param. Symbol No. D300 D301 D302 D303 D304 D305 Note Characteristics Min. Typical Max. Units — ±7.
PIC32MX3XX/4XX 29.2 AC Characteristics and Timing Parameters The information contained in this section defines PIC32MX3XX/4XX AC characteristics and timing parameters.
PIC32MX3XX/4XX TABLE 29-17: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp AC CHARACTERISTICS Param. Symbol No. OS10 FOSC OS11 Min. Typical(1) Max.
PIC32MX3XX/4XX TABLE 29-18: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.3V TO 3.6V) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typical Max.
PIC32MX3XX/4XX FIGURE 29-3: I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) Note: Refer to Figure 29-1 for load conditions. DO31 DO32 TABLE 29-21: I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param. No. Symbol DO31 TIOR DO32 Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp Min. Typical(1) Max. Units Conditions Port Output Rise Time — 5 15 ns VDD < 2.
PIC32MX3XX/4XX FIGURE 29-4: POWER-ON RESET TIMING CHARACTERISTICS Internal Voltage Regulator Enabled Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) VDD VPOR (TSYSDLY) SY02 Power Up Sequence (Note 2) CPU starts fetching code SY00 (TPU) (Note 1) Internal Voltage Regulator Enabled Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) VDD VPOR (TSYSDLY) SY02 Power Up Sequence (Note 2) SY00 (TPU) (Note 1) CPU starts fetching code SY10 (TOST) External VCORE Provided Clock Sources = (FR
PIC32MX3XX/4XX FIGURE 29-5: EXTERNAL RESET TIMING CHARACTERISTICS Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) MCLR TMCLR (SY20) BOR TBOR (SY30) (TSYSDLY) SY02 Reset Sequence CPU starts fetching code Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) (TSYSDLY) SY02 Reset Sequence CPU starts fetching code TOST (SY10) TABLE 29-22: RESETS TIMING Standard Operating Conditions: 2.3V to 3.
PIC32MX3XX/4XX FIGURE 29-6: TIMER1, 2, 3, 4, 5 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx11 Tx10 Tx15 Tx20 OS60 TMRx Note: Refer to Figure 29-1 for load conditions. TABLE 29-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp AC CHARACTERISTICS Param. No.
PIC32MX3XX/4XX TABLE 29-24: TIMER2, 3, 4, 5 EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param. No. Symbol Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp Characteristics(1) Min. Max. Units Conditions TB10 TTXH TxCK High Time Synchronous, with prescaler [(12.5 ns or 1TPB)/N] + 25 ns — ns TB11 TTXL TxCK Low Time Synchronous, with prescaler [(12.
PIC32MX3XX/4XX FIGURE 29-7: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS ICx IC10 IC11 IC15 Note: Refer to Figure 29-1 for load conditions. TABLE 29-25: INPUT CAPTURE MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Param. Symbol No. Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp Characteristics(1) Min. Max. Units Conditions IC10 TCCL ICx Input Low Time [(12.
PIC32MX3XX/4XX FIGURE 29-9: OC/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA/OCFB OC15 OCx OCx is tri-stated Note: Refer to Figure 29-1 for load conditions. TABLE 29-27: SIMPLE OC/PWM MODE TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp AC CHARACTERISTICS Param No.
PIC32MX3XX/4XX FIGURE 29-10: SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP11 SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 Bit 14 - - - - - -1 MSb SDOx SP31 SDIx LSb SP30 MSb In LSb In Bit 14 - - - -1 SP40 SP41 Note: Refer to Figure 29-1 for load conditions. TABLE 29-28: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.
PIC32MX3XX/4XX FIGURE 29-11: SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS SP36 SCKX (CKP = 0) SP11 SP10 SP21 SP20 SP20 SP21 SCKX (CKP = 1) SP35 Bit 14 - - - - - -1 MSb SDOX LSb SP30,SP31 SDIX MSb In SP40 Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure 29-1 for load conditions. TABLE 29-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.
PIC32MX3XX/4XX FIGURE 29-12: SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS SSX SP52 SP50 SCKX (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 MSb SDOX LSb Bit 14 - - - - - -1 SP51 SP30,SP31 SDIX MSb In SP40 Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure 29-1 for load conditions. TABLE 29-30: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.
PIC32MX3XX/4XX FIGURE 29-13: SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SSx SP50 SP52 SCKx (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 MSb SDOx Bit 14 - - - - - -1 LSb SP30,SP31 SDIx SDI MSb In SP40 SP51 Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure 29-1 for load conditions. TABLE 29-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.
PIC32MX3XX/4XX FIGURE 29-14: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM34 IM30 IM33 SDAx Stop Condition Start Condition Note: Refer to Figure 29-1 for load conditions. FIGURE 29-15: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM21 IM11 IM10 SCLx IM11 IM26 IM10 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure 29-1 for load conditions. © 2011 Microchip Technology Inc.
PIC32MX3XX/4XX TABLE 29-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp AC CHARACTERISTICS Param. Symbol No.
PIC32MX3XX/4XX FIGURE 29-16: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS34 IS31 IS30 IS33 SDAx Stop Condition Start Condition Note: Refer to Figure 29-1 for load conditions. FIGURE 29-17: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS21 IS11 IS10 SCLx IS30 IS26 IS31 IS25 IS33 SDAx In IS40 IS40 IS45 SDAx Out Note: Refer to Figure 29-1 for load conditions. © 2011 Microchip Technology Inc.
PIC32MX3XX/4XX TABLE 29-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp AC CHARACTERISTICS Param. No. IS10 IS11 IS20 IS21 IS25 IS26 IS30 IS31 IS33 IS34 IS40 IS45 IS50 Note Symbol TLO:SCL THI:SCL Characteristics Clock Low Time Clock High Time Min. Max. Units 100 kHz mode 4.7 — μs 400 kHz mode 1.
PIC32MX3XX/4XX TABLE 29-34: ADC MODULE SPECIFICATIONS AC CHARACTERISTICS Param. No. Symbol Characteristics Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp Min. Typical Max. Units Conditions Greater of VDD – 0.3 or 2.5 — Lesser of VDD + 0.3 or 3.6 V VSS — VSS + 0.
PIC32MX3XX/4XX TABLE 29-34: ADC MODULE SPECIFICATIONS (CONTINUED) AC CHARACTERISTICS Param. No. Symbol Characteristics Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp Min. Typical Max. Units Conditions ADC Accuracy – Measurements with Internal VREF+/VREFAD20d Nr Resolution AD21d INL Integral Nonlinearity — — <±1 LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.
PIC32MX3XX/4XX TABLE 29-35: 10-BIT ADC CONVERSION RATE PARAMETERS(2) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp ADC Speed 1 MIPS to 400 ksps(1) Sampling TAD RS Max Minimum Time Min 65 ns 132 ns 500Ω VDD ADC Channels Configuration 3.0V to 3.6V VREF- VREF+ ANx CHX SHA Up to 400 ksps 200 ns 200 ns ADC 5.0 kΩ 2.5V to 3.
PIC32MX3XX/4XX TABLE 29-36: ANALOG-TO-DIGITAL CONVERSION TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp AC CHARACTERISTICS Param. Symbol No. Characteristics Min. Typical(1) Max.
PIC32MX3XX/4XX FIGURE 29-18: ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc AD61 AD60 AD55 TSAMP AD55 CONV ADxIF Buffer(0) Buffer(1) 1 2 3 4 5 6 7 8 5 6 7 8 1 – Software sets ADxCON. SAMP to start sampling. 2 – Sampling starts after discharge period. TSAMP is described in Section 17.
PIC32MX3XX/4XX FIGURE 29-19: ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001) AD50 ADCLK Instruction Execution Set ADON SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc TSAMP TSAMP AD55 TCONV AD55 CONV ADxIF Buffer(0) Buffer(1) 1 2 3 4 5 6 7 3 4 5 6 8 3 4 1 – Software sets ADxCON. ADON to start AD operation. 2 – Sampling starts after discharge period. TSAMP is described in Section 17.
PIC32MX3XX/4XX FIGURE 29-20: PARALLEL SLAVE PORT TIMING CS PS5 RD PS6 WR PS4 PS7 PMD<7:0> PS1 PS3 PS2 TABLE 29-37: PARALLEL SLAVE PORT REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Typical Max.
PIC32MX3XX/4XX FIGURE 29-21: PARALLEL MASTER PORT READ TIMING DIAGRAM TPB TPB TPB TPB TPB TPB TPB TPB PB Clock PM4 Address PMA<13:18> PM6 PMD<7:0> Data Data Address<7:0> Address<7:0> PM2 PM7 PM3 PMRD PM5 PMWR PM1 PMALL/PMALH PMCS<2:1> TABLE 29-38: PARALLEL MASTER PORT READ TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp AC CHARACTERISTICS Param. Symbol No.
PIC32MX3XX/4XX FIGURE 29-22: PARALLEL MASTER PORT WRITE TIMING DIAGRAM TPB TPB TPB TPB TPB TPB TPB TPB PB Clock Address PMA<13:18> PM2 + PM3 Address<7:0> PMD<7:0> Data PM12 PM13 PMRD PM11 PMWR PM1 PMALL/PMALH PMCS<2:1> TABLE 29-39: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp AC CHARACTERISTICS Param. Symbol No.
PIC32MX3XX/4XX TABLE 29-40: OTG ELECTRICAL SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typ Max. Units Conditions USB313 VUSB USB Voltage 3.0 — 3.6 V Voltage on VUSB must be in this range for proper USB operation. USB315 VILUSB Input Low Voltage for USB Buffer — — 0.
PIC32MX3XX/4XX FIGURE 29-23: EJTAG TIMING CHARACTERISTICS TTCKeye TTCKhigh TTCKlow Trf TCK Trf TMS TDI TTsetup TThold Trf Trf TDO TRST* TTRST*low TTDOout TTDOzstate Defined Undefined Trf TABLE 29-41: EJTAG TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp AC CHARACTERISTICS Param. No. Description(1) Symbol Min. Max.
PIC32MX3XX/4XX NOTES: DS61143H-page 190 © 2011 Microchip Technology Inc.
PIC32MX3XX/4XX 30.0 PACKAGING INFORMATION 30.1 Package Marking Information 64-Lead TQFP (10x10x1 mm) Example PIC32MX360F 512H-80I/PT XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN e3 0510017 100-Lead TQFP (12x12x1 mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Example PIC32MX360F 256L-80I/PT e3 0510017 64-Lead QFN (9x9x0.9 mm) XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN PIC32MX360F 512H-80I/MR e3 0510017 121-Lead XBGA (10x10x1.1 mm) XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN Legend: XX...
PIC32MX3XX/4XX 30.2 Package Details The following sections give the technical details of the packages.
PIC32MX3XX/4XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2011 Microchip Technology Inc.
PIC32MX3XX/4XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS61143H-page 194 © 2011 Microchip Technology Inc.
PIC32MX3XX/4XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2011 Microchip Technology Inc.
PIC32MX3XX/4XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS61143H-page 196 © 2011 Microchip Technology Inc.
PIC32MX3XX/4XX ' ( # # !" #$ % & 3 & ' !& " & 4 && 255*** ' '5 # * !( 4 ! ! & 4 % & & # & D D1 e E E1 N b NOTE 1 1 23 NOTE 2 α c A φ L β A1 6 &! ' ! 7 ' &! 8"') % 7 7 # & 9 < & #! 77 . .
PIC32MX3XX/4XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS61143H-page 198 © 2011 Microchip Technology Inc.
PIC32MX3XX/4XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2011 Microchip Technology Inc.
PIC32MX3XX/4XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS61143H-page 200 © 2011 Microchip Technology Inc.
PIC32MX3XX/4XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2011 Microchip Technology Inc.
PIC32MX3XX/4XX NOTES: DS61143H-page 202 © 2011 Microchip Technology Inc.
PIC32MX3XX/4XX APPENDIX A: REVISION HISTORY Revision F (June 2009) Revision E (July 2008) This revision includes minor typographical and formatting changes throughout the data sheet text. • Updated the PIC32MX340F128H features in Table 1 to include 4 programmable DMA channels.
PIC32MX3XX/4XX TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section 26.0 “Special Features” Modified bit names and locations in Register 26-5 “DEVID: Device and Revision ID Register”. Replaced “TSTARTUP” with “TPU”, and “64-ms nominal delay” with “TPWRT”, in Section 26.3.1 “On-Chip Regulator and POR”.
PIC32MX3XX/4XX Revision G (April 2010) The revision includes the following global update: • Added Note 2 to the shaded table that appears at the beginning of each chapter. This new note provides information regarding the availability of registers and their associated bits. TABLE A-2: This revision also includes minor typographical and formatting changes throughout the data sheet text. Major updates are referenced by their respective section in the following table.
PIC32MX3XX/4XX TABLE A-2: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 29.0 “Electrical Characteristics” Update Description Updated the Absolute Maximum Ratings and added Note 3. Added Thermal Packaging Characteristics for the 121-pin XBGA package (see Table 29-3). Updated the conditions for parameters DC20, DC21, DC22 and DC23 in Table 29-5. Updated the comments for parameter D321 (CEFC) in Table 29-15.
PIC32MX3XX/4XX Revision H (May 2011) The revision includes the following global update: • All references to VDDCORE/VCAP have been changed to: VCORE/VCAP • Added references to the new V-Temp temperature range: -40ºC to +105ºC This revision also includes minor typographical and formatting changes throughout the data sheet text. Major updates are referenced by their respective section in the following table. TABLE A-3: MAJOR SECTION UPDATES Section Name Update Description Section 1.
PIC32MX3XX/4XX TABLE A-3: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 29.0 “Electrical Characteristics” Update Description Added the new V-Temp temperature range (-40ºC to +105ºC) to the heading of all specification tables. Updated the Ambient temperature under bias, updated the Voltage on any 5V tolerant pin with respect to VSS when VDD < 2.3V, and added Voltage on VBUS with respect to Vss in Absolute Maximum Ratings. Added the characteristic, DC5a to Operating MIPS vs.
PIC32MX3XX/4XX INDEX A M AC Characteristics ............................................................ 161 Internal RC Accuracy ................................................ 163 AC Electrical Specifications Parallel Master Port Read Requirements ................. 186 Parallel Master Port Write Requirements.................. 187 Parallel Slave Port Requirements ............................. 185 Assembler MPASM Assembler...................................................
PIC32MX3XX/4XX W Watchdog Timer Operation .................................................................. 137 WWW Address.................................................................. 209 WWW, On-Line Support...................................................... 19 DS61143H-page 210 © 2011 Microchip Technology Inc.
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PIC32MX3XX/4XX Product Identification System To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC32 MX 3XX F 512 H T - 80 I / PT - XXX Examples: PIC32MX320F032H-40I/PT: General purpose PIC32MX, 32 KB program memory, 64-pin, Industrial temperature, TQFP package.
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