Datasheet

© 2009-2012 Microchip Technology Inc. Preliminary DS70616F-page 327
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
bit 1 IDXIRQ: Status Flag for Index Event Status bit
1 = Index event has occurred
0 = No Index event has occurred
bit 0 IDXIEN: Index Input Event Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
REGISTER 17-3: QEIxSTAT: QEI STATUS REGISTER (CONTINUED)
Note 1: This status bit is only applicable to PIMOD<2:0> modes ‘011’ and ‘100’.