Datasheet

dsPIC33FJXXXGPX06A/X08A/X10A
DS70593D-page 86  2009-2012 Microchip Technology Inc.
TABLE 6-1: RESET FLAG BIT OPERATION
6.1 Clock Source Selection at Reset
If clock switching is enabled, the system clock source at
device Reset is chosen, as shown in Table 6-2. If clock
switching is disabled, the system clock source is always
selected according to the oscillator Configuration bits.
Refer to Section 9.0 “Oscillator Configuration” for
further details.
TABLE 6-2: OSCILLATOR SELECTION VS
TYPE OF RESET (CLOCK
SWITCHING ENABLED)
6.2 Device Reset Times
The Reset times for various types of device Reset are
summarized in Ta ble 6 - 3 . The system Reset signal,
SYSRST, is released after the POR and PWRT delay
times expire.
The time at which the device actually begins to execute
code also depends on the system oscillator delays,
which include the Oscillator Start-up Timer (OST) and
the PLL lock time. The OST and PLL lock times occur
in parallel with the applicable SYSRST
delay times.
The FSCM delay determines the time at which the
FSCM begins to monitor the system clock source after
the SYSRST
signal is released.
Flag Bit Setting Event Clearing Event
TRAPR (RCON<15>) Trap conflict event POR, BOR
IOPUWR (RCON<14>) Illegal opcode or uninitialized
W register access
POR, BOR
EXTR (RCON<7>) MCLR Reset POR
SWR (RCON<6>) RESET instruction POR, BOR
WDTO (RCON<4>) WDT time-out PWRSAV instruction, POR, BOR
SLEEP (RCON<3>) PWRSAV #SLEEP instruction POR, BOR
IDLE (RCON<2>) PWRSAV #IDLE instruction POR, BOR
BOR (RCON<1>) BOR, POR —
POR (RCON<0>) POR —
Note: All Reset flag bits may be set or cleared by the user software.
Reset Type Clock Source Determinant
POR Oscillator Configuration bits
(FNOSC<2:0>)
BOR
MCLR COSC Control bits
(OSCCON<14:12>)
WDTR
SWR