Datasheet

 2009-2012 Microchip Technology Inc. DS70593D-page 67
dsPIC33FJXXXGPX06A/X08A/X10A
4.2.7 SOFTWARE STACK
In addition to its use as a working register, the W15 register in the
dsPIC33FJXXXGPX06A/X08A/X10A devices is also used as a software Stack
Pointer. The Stack Pointer always points to the first available free word and
grows from lower to higher addresses. It pre-decrements for stack pops and
post-increments for stack pushes, as shown in Figure 4-6. For a PC push during
any CALL instruction, the MSb of the PC is zero-extended before the push,
ensuring that the MSb is always clear.
The Stack Pointer Limit register (SPLIM) associated with the Stack Pointer sets
an upper address boundary for the stack. SPLIM is uninitialized at Reset. As is
the case for the Stack Pointer, SPLIM<0> is forced to ‘0’ because all stack oper-
ations must be word-aligned. Whenever an EA is generated using W15 as a
source or destination pointer, the resulting address is compared with the value
in SPLIM. If the contents of the Stack Pointer (W15) and the SPLIM register are
equal and a push operation is performed, a stack error trap will not occur. The
stack error trap will occur on a subsequent push operation. Thus, for example,
if it is desirable to cause a stack error trap when the stack grows beyond
address 0x2000 in RAM, initialize the SPLIM with the value 0x1FFE.
Similarly, a Stack Pointer underflow (stack error) trap is generated when the
Stack Pointer address is found to be less than 0x0800. This prevents the stack
from interfering with the Special Function Register (SFR) space.
A write to the SPLIM register should not be immediately followed by an indirect
read operation using W15.
FIGURE 4-6: CALL STACK FRAME
4.2.8 DATA RAM PROTECTION FEATURE
The dsPIC33F product family supports Data RAM protection features which
enable segments of RAM to be protected when used in conjunction with Boot
and Secure Code Segment Security. BSRAM (Secure RAM segment for BS) is
accessible only from the Boot Segment Flash code when enabled. SSRAM
(Secure RAM segment for RAM) is accessible only from the Secure Segment
Flash code when enabled. See Table 4-1 for an overview of the BSRAM and
SSRAM SFRs.
4.3 Instruction Addressing Modes
The addressing modes in Table 4- 35 form the basis of the addressing modes
optimized to support the specific features of individual instructions. The
addressing modes provided in the MAC class of instructions are somewhat dif-
ferent from those in the other instruction types.
4.3.1 FILE REGISTER INSTRUCTIONS
Most file register instructions use a 13-bit address field (f) to directly address
data present in the first 8192 bytes of data memory (Near Data Space). Most
file register instructions employ a working register, W0, which is denoted as
WREG in these instructions. The destination is typically either the same file reg-
Note: A PC push during exception processing
concatenates the SRL register to the MSb
of the PC prior to the push.
<Free Word>
PC<15:0>
000000000
015
W15 (before CALL)
W15 (after CALL)
Stack Grows Towards
Higher Address
0x0000
PC<22:16>
POP : [--W15]
PUSH : [W15++]