Datasheet

2009-2012 Microchip Technology Inc. DS70593D-page 355
dsPIC33FJXXXGPX06A/X08A/X10A
PORTA
Register Map............................................................... 64
PORTB
Register Map............................................................... 64
PORTC
Register Map............................................................... 65
PORTD
Register Map............................................................... 65
PORTE
Register Map............................................................... 65
PORTF
Register Map............................................................... 65
PORTG
Register Map............................................................... 66
Power-Saving Features .................................................... 155
Clock Frequency and Switching................................ 155
Program Address Space..................................................... 39
Construction................................................................ 72
Data Access from Program Memory
Using Program Space Visibility........................... 75
Data Access from Program Memory
Using Table Instructions ..................................... 74
Data Access from, Address Generation...................... 73
Memory Map............................................................... 39
Table Read Instructions
TBLRDH ............................................................. 74
TBLRDL .............................................................. 74
Visibility Operation ...................................................... 75
Program Memory
Interrupt Vector ........................................................... 40
Organization................................................................ 40
Reset Vector ............................................................... 40
R
Reader Response ............................................................. 358
Registers
ADxCHS0 (ADCx Input Channel 0 Select................. 247
ADxCHS123 (ADCx Input Channel 1, 2, 3 Select) ... 246
ADxCON1 (ADCx Control 1)..................................... 241
ADxCON2 (ADCx Control 2)..................................... 243
ADxCON3 (ADCx Control 3)..................................... 244
ADxCON4 (ADCx Control 4)..................................... 245
ADxCSSH (ADCx Input Scan Select High)............... 248
ADxCSSL (ADCx Input Scan Select Low) ................ 248
ADxPCFGH (ADCx Port Configuration High) ........... 249
ADxPCFGL (ADCx Port Configuration Low)............. 249
CiBUFPNT1 (ECAN Filter 0-3 Buffer Pointer)........... 215
CiBUFPNT2 (ECAN Filter 4-7 Buffer Pointer)........... 216
CiBUFPNT3 (ECAN Filter 8-11 Buffer Pointer)......... 217
CiBUFPNT4 (ECAN Filter 12-15 Buffer Pointer)....... 218
CiCFG1 (ECAN Baud Rate Configuration 1) ............ 212
CiCFG2 (ECAN Baud Rate Configuration 2) ............ 213
CiCTRL1 (ECAN Control 1) ...................................... 204
CiCTRL2 (ECAN Control 2) ...................................... 205
CiEC (ECAN Transmit/Receive Error Count)............ 211
CiFCTRL (ECAN FIFO Control)................................ 207
CiFEN1 (ECAN Acceptance Filter Enable) ............... 214
CiFIFO (ECAN FIFO Status)..................................... 208
CiFMSKSEL1 (ECAN Filter 7-0 Mask
Selection).................................................. 220, 221
CiINTE (ECAN Interrupt Enable) .............................. 210
CiINTF (ECAN Interrupt Flag)................................... 209
CiRXFnEID (ECAN Acceptance Filter n
Extended Identifier)........................................... 219
CiRXFnSID (ECAN Acceptance Filter n
Standard Identifier) ........................................... 219
CiRXFUL1 (ECAN Receive Buffer Full 1)................. 223
CiRXFUL2 (ECAN Receive Buffer Full 2)................. 223
CiRXMnEID (ECAN Acceptance Filter Mask n
Extended Identifier) .......................................... 222
CiRXMnSID (ECAN Acceptance Filter Mask n
Standard Identifier)........................................... 222
CiRXOVF1 (ECAN Receive Buffer Overflow 1)........ 224
CiRXOVF2 (ECAN Receive Buffer Overflow 2)........ 224
CiTRBnDLC (ECAN Buffer n Data
Length Control)................................................. 227
CiTRBnDm (ECAN Buffer n Data Field Byte m) ....... 227
CiTRBnEID (ECAN Buffer n Extended Identifier) ..... 226
CiTRBnSID (ECAN Buffer n Standard Identifier)...... 226
CiTRBnSTAT (ECAN Receive Buffer n Status)........ 228
CiTRmnCON (ECAN TX/RX Buffer m Control) ........ 225
CiVEC (ECAN Interrupt Code) ................................. 206
CLKDIV (Clock Divisor) ............................................ 150
CORCON (Core Control) ...................................... 32, 94
DCICON1 (DCI Control 1) ........................................ 231
DCICON2 (DCI Control 2) ........................................ 232
DCICON3 (DCI Control 3) ........................................ 233
DCISTAT (DCI Status) ............................................. 234
DMACS0 (DMA Controller Status 0) ........................ 141
DMACS1 (DMA Controller Status 1) ........................ 143
DMAxCNT (DMA Channel x Transfer Count) ........... 140
DMAxCON (DMA Channel x Control)....................... 137
DMAxPAD (DMA Channel x Peripheral Address) .... 140
DMAxREQ (DMA Channel x IRQ Select) ................. 138
DMAxSTA (DMA Channel x RAM Start
Address A)........................................................ 139
DMAxSTB (DMA Channel x RAM Start
Address B)........................................................ 139
DSADR (Most Recent DMA RAM Address) ............. 144
I2CxCON (I2Cx Control)........................................... 190
I2CxMSK (I2Cx Slave Mode Address Mask)............ 194
I2CxSTAT (I2Cx Status) ........................................... 192
ICxCON (Input Capture x Control)............................ 176
IEC0 (Interrupt Enable Control 0) ............................. 106
IEC1 (Interrupt Enable Control 1) ............................. 108
IEC2 (Interrupt Enable Control 2) ............................. 110
IEC3 (Interrupt Enable Control 3) ............................. 112
IEC4 (Interrupt Enable Control 4) ............................. 113
IFS0 (Interrupt Flag Status 0) ..................................... 98
IFS1 (Interrupt Flag Status 1) ................................... 100
IFS2 (Interrupt Flag Status 2) ................................... 102
IFS3 (Interrupt Flag Status 3) ................................... 104
IFS4 (Interrupt Flag Status 4) ................................... 105
INTCON1 (Interrupt Control 1) ................................... 95
INTCON2 (Interrupt Control 2) ................................... 97
INTTREG Interrupt Control and Status Register ...... 132
IPC0 (Interrupt Priority Control 0) ............................. 114
IPC1 (Interrupt Priority Control 1) ............................. 115
IPC10 (Interrupt Priority Control 10) ......................... 124
IPC11 (Interrupt Priority Control 11) ......................... 125
IPC12 (Interrupt Priority Control 12) ......................... 126
IPC13 (Interrupt Priority Control 13) ......................... 127
IPC14 (Interrupt Priority Control 14) ......................... 128
IPC15 (Interrupt Priority Control 15) ......................... 129
IPC16 (Interrupt Priority Control 16) ......................... 130
IPC17 (Interrupt Priority Control 17) ......................... 131
IPC2 (Interrupt Priority Control 2) ............................. 116
IPC3 (Interrupt Priority Control 3) ............................. 117
IPC4 (Interrupt Priority Control 4) ............................. 118
IPC5 (Interrupt Priority Control 5) ............................. 119
IPC6 (Interrupt Priority Control 6) ............................. 120