Datasheet

 2009-2012 Microchip Technology Inc. DS70593D-page 349
dsPIC33FJXXXGPX06A/X08A/X10A
Revision C (March 2011)
This revision includes typographical and formatting
changes throughout the data sheet text. In addition, all
instances of V
DDCORE have been removed.
All other major changes are referenced by their
respective section in the following table.
TABLE B-2: MAJOR SECTION UPDATES
Section Name Update Description
Section 2.0 “Guidelines for Getting Started
with 16-Bit Digital Signal Controllers”
Updated the title of Section 2.3 “CPU Logic Filter Capacitor
Connection (VCAP)”.
The frequency limitation for device PLL start-up conditions was
updated in Section 2.7 “Oscillator Value Conditions on Device
Start-up”.
The second paragraph in Section 2.9 “Unused I/Os” was updated.
Section 4.0 “Memory Organization” The All Resets values for the following SFRs in the Timer Register
Map were changed (see Table 4-6):
•TMR1
•TMR2
•TMR3
•TMR4
•TMR5
•TMR6
•TMR7
•TMR8
•TMR9
Section 9.0 “Oscillator Configuration” Added Note 3 to the OSCCON: Oscillator Control Register (see
Register 9-1).
Added Note 2 to the CLKDIV: Clock Divisor Register (see
Register 9-2).
Added Note 1 to the PLLFBD: PLL Feedback Divisor Register (see
Register 9-3).
Added Note 2 to the OSCTUN: FRC Oscillator Tuning Register (see
Register 9-4).
Section 21.0 “10-Bit/12-Bit
Analog-to-Digital Converter (ADC)”
Updated the V
REFL references in the ADC1 module block diagram
(see Figure 21-1).
Section 22.0 “Special Features” Added a new paragraph and removed the third paragraph in
Section 22.1 “Configuration Bits”.
Added the column “RTSP Effects” to the Configuration Bits
Descriptions (see Table 22-2).