Datasheet

dsPIC33FJXXXGPX06A/X08A/X10A
DS70593D-page 348  2009-2012 Microchip Technology Inc.
APPENDIX B: REVISION HISTORY
Revision A (April 2009)
This is the initial released version of the document.
Revision B (October 2009)
The revision includes the following global update:
• Added Note 2 to the shaded table that appears at
the beginning of each chapter. This new note
provides information regarding the availability of
registers and their associated bits
This revision also includes minor typographical and
formatting changes throughout the data sheet text.
All other major changes are referenced by their
respective section in the following table.
TABLE B-1: MAJOR SECTION UPDATES
Section Name Update Description
“High-Performance, 16-Bit Digital Signal
Controllers”
Added information on high temperature operation (see “Operating
Range”).
Section 10.0 “Power-Saving Features” Updated the last paragraph to clarify the number of cycles that occur
prior to the start of instruction execution (see Section 10.2.2 “Idle
Mode”).
Section 11.0 “I/O Ports” Changed the reference to digital-only pins to 5V tolerant pins in the
second paragraph of Section 11.2 “Open-Drain Configuration”.
Section 18.0 “Universal Asynchronous
Receiver Transmitter (UART)”
Updated the two baud rate range features to: 10 Mbps to 38 bps at
40 MIPS.
Section 21.0 “10-Bit/12-Bit
Analog-to-Digital Converter (ADC)”
Updated the ADCx block diagram (see Figure 21-1).
Section 22.0 “Special Features” Updated the second paragraph and removed the fourth paragraph in
Section 22.1 “Configuration Bits”.
Updated the Device Configuration Register Map (see Table 22-1).
Added the FPWRT<2:0> bit field for the FWDT register to the
Configurative Bits Description table (see Table 22-1).
Section 25.0 “Electrical Characteristics” Updated the Absolute Maximum Ratings for high temperature and
added Note 4.
Updated Power-Down Current parameters DC60d, DC60a, DC60b,
and DC60d (see Table 25-7).
Added I2Cx Bus Data Timing Requirements (Master Mode)
parameter IM51 (see Table 25-36).
Updated the SPIx Module Slave Mode (CKE = 1) Timing
Characteristics (see Figure 25-12).
Updated the Internal LPRC Accuracy parameters (see Table 25-19).
Updated the ADC Module Specifications (12-bit Mode) parameters
AD23a and AD24a (see Table 25-42).
Updated the ADC Module Specifications (10-bit Mode) parameters
AD23b and AD24b (see Table 25-43).
Section 26.0 “High Temperature Electrical
Characteristics”
Added new chapter with high temperature specifications.
“Product Identification System” Added the “H” definition for high temperature.