Datasheet

dsPIC33FJXXXGPX06A/X08A/X10A
DS70593D-page 310  2009-2012 Microchip Technology Inc.
FIGURE 25-22: DCI MODULE (AC-LINK MODE) TIMING CHARACTERISTICS
TABLE 25-39: DCI MODULE (AC-LINK MODE) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C
-40°C  T
A  +125°C for Extended
Param
No.
Symbol Characteristic
(1,2)
Min Typ
(3)
Max Units Conditions
CS60 T
BCLKL BIT_CLK Low Time 36 40.7 45 ns —
CS61 T
BCLKH BIT_CLK High Time 36 40.7 45 ns —
CS62 T
BCLK BIT_CLK Period — 81.4 — ns Bit clock is input
CS65 T
SACL Input Setup Time to
Falling Edge of BIT_CLK
— — 10 ns —
CS66 T
HACL Input Hold Time from
Falling Edge of BIT_CLK
— — 10 ns —
CS70 TSYNCLO SYNC Data Output Low Time — 19.5 — s Note 1
CS71 TSYNCHI SYNC Data Output High Time — 1.3 — s Note 1
CS72 T
SYNC SYNC Data Output Period — 20.8 — s Note 1
CS75 T
RACL Rise Time, SYNC, SDATA_OUT — 10 25 ns CLOAD = 50 pF, VDD = 5V
CS76 T
FACL Fall Time, SYNC, SDATA_OUT — 10 25 ns CLOAD = 50 pF, VDD = 5V
CS77 T
RACL Rise Time, SYNC, SDATA_OUT — — 30 ns CLOAD = 50 pF, VDD = 3V
CS78 T
FACL Fall Time, SYNC, SDATA_OUT — — 30 ns CLOAD = 50 pF, VDD = 3V
CS80 T
OVDACL Output Valid Delay from Rising
Edge of BIT_CLK
— — 15 ns —
Note 1: These parameters are characterized but not tested in manufacturing.
2: These values assume BIT_CLK frequency is 12.288 MHz.
3: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
SYNC
BIT_CLK
SDOx
SDIx
CS61 CS60
CS65 CS66
CS80
CS21
MSb In
CS75
LSb
CS76
(COFS)
(CSCK)
LSb
MSb
CS72
CS71
CS70
CS76
CS75
(CSDO)
(CSDI)
CS62
CS20