Datasheet

dsPIC33FJXXXGPX06A/X08A/X10A
DS70593D-page 238  2009-2012 Microchip Technology Inc.
FIGURE 21-1: ADCx MODULE BLOCK DIAGRAM
SAR ADC
S/H0
S/H1
ADC1BUF0
AN0
ANy
(3)
AN1
VREFL
CH0SB<4:0>
CH0NA
CH0NB
+
-
AN0
AN3
CH123SA
AN9
VREFL
CH123SB
CH123NA
CH123NB
AN6
+
-
S/H2
AN1
AN4
CH123SA
AN10
VREFL
CH123SB
CH123NA
CH123NB
AN7
+
-
S/H3
AN2
AN5
CH123SA
AN11
VREFL
CH123SB
CH123NA
CH123NB
AN8
+
-
CH1
(2)
CH0
CH2
(2)
CH3
(2)
CH0SA<4:0>
CHANNEL
SCAN
CSCNA
Alternate
Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs.
2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation.
3: For 64-pin devices, y = 17; for 80-pin devices, y = 23; for 100-pin devices, y = 31; for ADC2, y = 15.
Input Selection
V
REFH
VREFL
AVDD
AVSS
VREF-
(1)
VREF+
(1)
VCFG<2:0>