Datasheet

 2009-2012 Microchip Technology Inc. DS70593D-page 229
dsPIC33FJXXXGPX06A/X08A/X10A
20.0 DATA CONVERTER
INTERFACE (DCI) MODULE
20.1 Module Introduction
The dsPIC33FJXXXGPX06A/X08A/X10A Data Con-
verter Interface (DCI) module allows simple interfacing
of devices, such as audio coder/decoders (Codecs),
ADC and D/A converters. The following interfaces are
supported:
• Framed Synchronous Serial Transfer (Single or
Multi-Channel)
• Inter-IC Sound (I
2
S) Interface
• AC-Link Compliant mode
The DCI module provides the following general
features:
• Programmable word size up to 16 bits
• Supports up to 16 time slots, for a maximum
frame size of 256 bits
• Data buffering for up to 4 samples without CPU
overhead
20.2 Module I/O Pins
There are four I/O pins associated with the module.
When enabled, the module controls the data direction
of each of the four pins.
20.2.1 CSCK PIN
The CSCK pin provides the serial clock for the DCI
module. The CSCK pin may be configured as an input
or output using the CSCKD control bit in the DCICON1
SFR. When configured as an output, the serial clock is
provided by the dsPIC33FJXXXGPX06A/X08A/X10A.
When configured as an input, the serial clock must be
provided by an external device.
20.2.2 CSDO PIN
The Serial Data Output (CSDO) pin is configured as an
output only pin when the module is enabled. The
CSDO pin drives the serial bus whenever data is to be
transmitted. The CSDO pin is tri-stated, or driven to ‘0’,
during CSCK periods when data is not transmitted
depending on the state of the CSDOM control bit. This
allows other devices to place data on the serial bus
during transmission periods not used by the DCI
module.
20.2.3 CSDI PIN
The Serial Data Input (CSDI) pin is configured as an
input only pin when the module is enabled.
20.2.3.1 COFS Pin
The Codec Frame Synchronization (COFS) pin is used
to synchronize data transfers that occur on the CSDO
and CSDI pins. The COFS pin may be configured as an
input or an output. The data direction for the COFS pin
is determined by the COFSD control bit in the
DCICON1 register.
The DCI module accesses the shadow registers while
the CPU is in the process of accessing the memory
mapped buffer registers.
20.2.4 BUFFER DATA ALIGNMENT
Data values are always stored left justified in the
buffers since most Codec data is represented as a
signed 2’s complement fractional number. If the
received word length is less than 16 bits, the unused
Least Significant bits in the Receive Buffer registers are
set to ‘0’ by the module. If the transmitted word length
is less than 16 bits, the unused LSbs in the Transmit
Buffer register are ignored by the module. The word
length setup is described in subsequent sections of this
document.
20.2.5 TRANSMIT/RECEIVE SHIFT
REGISTER
The DCI module has a 16-bit shift register for shifting
serial data in and out of the module. Data is shifted in/
out of the shift register, MSb first, since audio PCM data
is transmitted in signed 2’s complement format.
20.2.6 DCI BUFFER CONTROL
The DCI module contains a buffer control unit for
transferring data between the shadow buffer memory
and the Serial Shift register. The buffer control unit is a
simple 2-bit address counter that points to word loca-
tions in the shadow buffer memory. For the receive
memory space (high address portion of DCI buffer
memory), the address counter is concatenated with a
‘0’ in the MSb location to form a 3-bit address. For the
transmit memory space (high portion of DCI buffer
memory), the address counter is concatenated with a
‘1’ in the MSb location.
Note 1: This data sheet summarizes the features
of the dsPIC33FJXXXGPX06A/X08A/
X10A family of devices. However, it is not
intended to be a comprehensive refer-
ence source. To complement the infor-
mation in this data sheet, refer to Section
20. “Data Converter Interface (DCI)”
(DS70288) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Note: The DCI buffer control unit always
accesses the same relative location in the
transmit and receive buffers, so only one
address counter is provided.