Datasheet

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
DS70616F-page 596 Preliminary © 2009-2012 Microchip Technology Inc.
Section 17.0 “Quadrature
Encoder Interface (QEI) Module
(dsPIC33EPXXXMU806/810/814
Devices Only)”
Reordered the bit values for the OUTFNC<1:0> bits and updated the default
POR bit value to ‘x’ for the HOME, INDEX, QEB, and QEA bits in the QEI I/O
Control Register (see Register 17-2).
Section 23.0 “10-bit/12-bit
Analog-to-Digital Converter
(ADC)”
Updated VREFL in the ADC1 and ADC2 Module Block Diagram (see
Figure 23-1).
Section 25.0 “Comparator
Module”
Added Note 1 to the Comparator I/O Operating Modes (see Figure 25-1).
Removed the CLPWR bit (CMxCON<12>) (see Register 25-2).
Section 29.0 “Special Features” Added a new first paragraph to Section 29.1 “Configuration Bits”
Section 30.0 “Instruction Set
Summary”
The following instructions have been updated (see Table 30-2):
•BRA
•CALL
• CPBEQ
• CPBGT
• CPBLT
• CPBNE
•GOTO
• MOVPAG
•MUL
• RCALL
• RETFIE
• RETLW
• RETURN
• TBLRDH
• TBLRDL
Section 32.0 “Electrical
Characteristics”
Updated the Typical and Maximum values for DC Characteristics: Operating
Current (I
DD) (see Table 32-5).
Updated the Typical and Maximum values for DC Characteristics: Idle Current
(I
IDLE) (see Table 32-6).
Updated the Maximum values for DC Characteristics: Power-down Current
(I
PD) (see Table 32-7).
Updated the Maximum values for DC Characteristics: Doze Current (I
DOZE)
(see Table 32-8).
Updated the parameter numbers for Internal FRC Accuracy (see Table 32-19).
Updated the parameter numbers and the Typical value for parameter F21b for
Internal RC Accuracy (see Table 32-20).
Updated the Minimum value for PM6 and the Typical and Maximum values for
PM7 in Parallel Master Port Read Requirements (see Table 32-52).
Added DMA Module Timing Requirements (see Table 32-54).
TABLE A-1: MAJOR SECTION UPDATES (CONTINUED)
Section Name Update Description