Datasheet

© 2009-2012 Microchip Technology Inc. Preliminary DS70616F-page 595
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
Section 7.0 “Interrupt Controller” Added the VAR bit (CORCON<15>) to the Core Control Register (see
Register 7-2)
Changed the default POR value for the GIE bit (INTCON2<15) to R/W-1 (see
Register 7-4).
Changed the VECNUM<7:0> = 11111111 pending interrupt vector number to
263 in the Interrupt Control and Status Register (see Register 7-7).
Section 8.0 “Direct Memory
Access (DMA)”
Updated Section 8.1 “DMAC Registers”.
Updated DMA Controller in Figure 8-1.
Added Note 1 to the DMA Channel x Peripheral Address Register (see
Register 8-7).
Added Note 1 and Note 2 to the DMA Channel x Transfer Count Register (see
Register 8-8).
Updated all RQCOLx bit definitions, changing Peripheral Write to Transfer
Request in the DMA Request Collision Status Register (see Register 8-12).
Section 9.0 “Oscillator
Configuration”
Added the Reference Oscillator Control Register (see Register 9-7).
Added Note 3 and 4 to the CLKDIV Register (see Register 9-2)
Section 10.0 “Power-Saving
Features”
Added the DCIMD and C2MD bits to the Peripheral Module Disable Control
Register 1 (see Register 10-1)
Added the IC6MD, IC5MD, IC4MD, IC3MD, OC8MD, OC7MD, OC6MD, and
OC5MD bits to the Peripheral Module Disable Control Register 2 (see
Register 10-2)
Added the T9MD, T8MD, T7MD, and T6MD bits and removed the DSC1MD bit
in the Peripheral Module Disable Control Register 3 (see Register 10-3).
Added the REFOMD bit (PMD4<3>) to the Peripheral Module Disable Control
Register 4 (see Register 10-4).
Section 11.0 “I/O Ports” Updated the first paragraph of Section 11.2 “Configuring Analog and Digital
Port Pins”.
Updated the PWM Fault, Dead Time Compensation, and Synch Input register
numbers of the Selectable Input Sources (see Table 11-2).
Removed RPINR22 register.
Bit names and definitions were modified in the following registers:
• Peripheral Pin Select Input Register 37 (see Register 11-37)
• Peripheral Pin Select Input Register 38 (see Register 11-38)
• Peripheral Pin Select Input Register 39 (see Register 11-39)
• Peripheral Pin Select Input Register 40 (see Register 11-40)
• Peripheral Pin Select Input Register 41 (see Register 11-41)
• Peripheral Pin Select Input Register 42 (see Register 11-42)
• Peripheral Pin Select Input Register 43 (see Register 11-43)
Section 12.0 “Timer1” Added Note in Register 12-1.
Section 14.0 “Input Capture” Added Note 1 to the Input Capture Block Diagram (see Figure 14-1).
Section 15.0 “Output Compare” Added Note 1 to the Output Compare Module Block Diagram (see Figure 15-1).
Added Note 2 to the Output Compare x Control Register 2 (see Register 15-2).
Section 16.0 “High-Speed PWM
Module (dsPIC33EPXXXMU806/
810/814 Devices Only)”
Added Comparator bit values for the CLSRC<4:0> and FLTSRC<4:0> bits in
the PWM Fault Current-Limit Control Register (see Register 16-21).
TABLE A-1: MAJOR SECTION UPDATES (CONTINUED)
Section Name Update Description