Datasheet

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
DS70616F-page 562 Preliminary © 2009-2012 Microchip Technology Inc.
TABLE 32-60: DCI MODULE (AC-LINK MODE) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ T
A ≤ +125°C for Extended
Param. Symbol Characteristic
(1,2)
Min. Typ.
(3)
Max. Units Conditions
CS60 TBCLKL BIT_CLK Low Time 36 40.7 45 ns —
CS61 T
BCLKH BIT_CLK High Time 36 40.7 45 ns —
CS62 T
BCLK BIT_CLK Period — 81.4 — ns Bit clock is input
CS65 T
SACL Input Setup Time to
Falling Edge of BIT_CLK
— — 10 ns —
CS66 T
HACL Input Hold Time from
Falling Edge of BIT_CLK
— — 10 ns —
CS70 T
SYNCLO SYNC Data Output Low Time — 19.5 — μs—
CS71 T
SYNCHI SYNC Data Output High Time — 1.3 — μs—
CS72 T
SYNC SYNC Data Output Period — 20.8 — μs—
CS77 T
RACL Rise Time, SYNC, SDATA_OUT — — — ns See parameter DO32
CS78 T
FACL Fall Time, SYNC, SDATA_OUT — — — ns See parameter DO31
CS80 T
OVDACL Output Valid Delay from Rising
Edge of BIT_CLK
— — 15 ns —
Note 1: These parameters are characterized but not tested in manufacturing.
2: These values assume BIT_CLK frequency is 12.288 MHz.
3: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.