Datasheet

© 2009-2012 Microchip Technology Inc. Preliminary DS70616F-page 489
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
72 SL SL f f = Left Shift f 1 1 C,N,OV,Z
SL f,WREG WREG = Left Shift f 1 1 C,N,OV,Z
SL Ws,Wd Wd = Left Shift Ws 1 1 C,N,OV,Z
SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N,Z
SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N,Z
73 SUB SUB Acc
(1)
Subtract Accumulators 1 1 OA,OB,OAB,
SA,SB,SAB
SUB f f = f – WREG 1 1 C,DC,N,OV,Z
SUB f,WREG WREG = f – WREG 1 1 C,DC,N,OV,Z
SUB #lit10,Wn Wn = Wn – lit10 1 1 C,DC,N,OV,Z
SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C,DC,N,OV,Z
SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C,DC,N,OV,Z
74 SUBB
SUBB f f = f – WREG – (C
)11
C,DC,N,OV,Z
SUBB f,WREG WREG = f – WREG – (C
)11
C,DC,N,OV,Z
SUBB #lit10,Wn Wn = Wn – lit10 – (C
)11
C,DC,N,OV,Z
SUBB Wb,Ws,Wd Wd = Wb – Ws – (C
)11
C,DC,N,OV,Z
SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C
)11
C,DC,N,OV,Z
75 SUBR SUBR f f = WREG – f 1 1 C,DC,N,OV,Z
SUBR f,WREG WREG = WREG – f 1 1 C,DC,N,OV,Z
SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C,DC,N,OV,Z
SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 C,DC,N,OV,Z
76 SUBBR SUBBR f f = WREG – f – (C
)11
C,DC,N,OV,Z
SUBBR f,WREG WREG = WREG – f – (C
)11
C,DC,N,OV,Z
SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C
)11
C,DC,N,OV,Z
SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C
)11
C,DC,N,OV,Z
77 SWAP SWAP.b Wn Wn = nibble swap Wn 1 1 None
SWAP Wn Wn = byte swap Wn 1 1 None
78 TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 5 None
79 TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 5 None
80 TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None
81 TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None
82 ULNK ULNK Unlink Frame Pointer 1 1 SFA
83 XOR XOR f f = f .XOR. WREG 1 1 N,Z
XOR f,WREG WREG = f .XOR. WREG 1 1 N,Z
XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N,Z
XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N,Z
XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N,Z
84 ZE ZE Ws,Wnd Wnd = Zero-extend Ws 1 1 C,Z,N
TABLE 30-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic
Assembly Syntax Description
# of
Words
# of
Cycles
(2)
Status Flags
Affected
Note 1: This instruction is available in dsPIC33EPXXX(GP/MC/MU)806/810/814 devices only.
2: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.