Datasheet

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
DS70616F-page 474 Preliminary © 2009-2012 Microchip Technology Inc.
TABLE 29-2: CONFIGURATION BITS DESCRIPTION
Bit Field Register RTSP Effect Description
GSSK<1:0> FGS Immediate General Segment Key bits.
These bits must be set to ‘00’ if GWRP = 1 and GSS = 1.
These bits must be set to ‘11’ for any other value of the GWRP and
GSS bits.
Any mismatch between either the GWRP or GSS bits, and the
GSSK bits (as described above), will result in code protection
getting enabled for the General Segment. A Flash bulk erase will be
required to unlock the device.
GSS FGS Immediate General Segment Code-Protect bit
1 = User program memory is not code-protected
0 = User program memory is code-protected
GWRP FGS Immediate General Segment Write-Protect bit
1 = User program memory is not write-protected
0 = User program memory is write-protected
IESO FOSCSEL Immediate Two-speed Oscillator Start-up Enable bit
1 = Start-up device with FRC, then automatically switch to the
user-selected oscillator source when ready
0 = Start-up device with user-selected oscillator source
FNOSC<2:0> FOSCSEL If clock switch
is enabled, the
RTSP effect is
on any device
Reset;
otherwise,
immediate
Initial Oscillator Source Selection bits
111 = Internal Fast RC (FRC) Oscillator with postscaler
110 = Internal Fast RC (FRC) Oscillator with divide-by-16
101 = LPRC Oscillator
100 = Secondary (LP) Oscillator
011 = Primary (XT, HS, EC) Oscillator with PLL
010 = Primary (XT, HS, EC) Oscillator
001 = Internal Fast RC (FRC) Oscillator with PLL
000 = FRC Oscillator
FCKSM<1:0> FOSC Immediate Clock Switching Mode bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
IOL1WAY FOSC Immediate Peripheral pin select configuration
1 = Allow only one reconfiguration
0 = Allow multiple reconfigurations
OSCIOFNC FOSC Immediate OSC2 Pin Function bit (except in XT and HS modes)
1 = OSC2 is clock output
0 = OSC2 is general purpose digital I/O pin
POSCMD<1:0> FOSC Immediate Primary Oscillator Mode Select bits
11 = Primary Oscillator disabled
10 = HS Crystal Oscillator mode
01 = XT Crystal Oscillator mode
00 = EC (External Clock) mode
FWDTEN FWDT Immediate Watchdog Timer Enable bit
1 = Watchdog Timer always enabled (LPRC Oscillator cannot be
disabled. Clearing the SWDTEN bit in the RCON register has no
effect.)
0 = Watchdog Timer enabled/disabled by user software (LPRC can
be disabled by clearing the SWDTEN bit in the RCON register)
Note 1: BOR should always be enabled for proper operation (BOREN = 1
).
2: This register can only be modified when Code Protection and Write Protection are disabled for both the
General and Auxiliary Segments (APL = 1, AWRP = 1, APLK = 0, GSS = 1, GWRP = 1, and GSSK = 0).