Datasheet

© 2009-2012 Microchip Technology Inc. Preliminary DS70616F-page 457
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
27.0 PROGRAMMABLE CYCLIC
REDUNDANCY CHECK (CRC)
GENERATOR
The programmable CRC generator offers the following
features:
• User-programmable (up to 32nd order)
polynomial CRC equation
• Interrupt output
• Data FIFO
The programmable CRC generator provides a
hardware-implemented method of quickly generating
checksums for various networking and security
applications. It offers the following features:
• User-programmable CRC polynomial equation,
up to 32 bits
• Programmable shift direction (little or big-endian)
• Independent data and polynomial lengths
• Configurable Interrupt output
• Data FIFO
A simplified block diagram of the CRC generator is
shown in Figure 27-1. A simple version of the CRC shift
engine is shown in Figure 27-2.
FIGURE 27-1: CRC BLOCK DIAGRAM
FIGURE 27-2: CRC SHIFT ENGINE DETAIL
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXX(GP/MC/MU)806/
810/814 and PIC24EPXXX(GP/GU)810/
814 families of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 27. “Pro-
grammable Cyclic Redundancy Check
(CRC)” (DS70346) of the “dsPIC33E/
PIC24E Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Variable FIFO
(4x32, 8x16 or 16x8)
CRCDATH
CRCDATL
Shift Buffer
CRC Shift Engine
CRCWDATH CRCWDATL
LENDIAN
10
CRCISEL
1
0
FIFO Empty Event
Shift Complete Event
Set CRCIF
2 * FP Shift Clock
CRCWDATH CRCWDATL
Bit 0 Bit 1 Bit n
(2)
X(1)
(1)
Read/Write Bus
Shift Buffer
Data
Bit 2
X(2)
(1)
X(n)
(1)
Note 1: Each XOR stage of the shift engine is programmable. See text for details.
2: Polynomial length n is determined by ([PLEN<4:0>] + 1).