Datasheet

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
DS70616F-page 450 Preliminary © 2009-2012 Microchip Technology Inc.
bit 7-0 CAL<7:0>: RTCC Drift Calibration bits
01111111 = Maximum positive adjustment; adds 508 RTCC clock pulses every one minute
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00000001 = Minimum positive adjustment; adds four RTCC clock pulses every one minute
00000000 = No adjustment
11111111 = Minimum negative adjustment; subtracts four RTCC clock pulses every one minute
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10000000 = Maximum negative adjustment; subtracts 512 RTCC clock pulses every one minute
REGISTER 26-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION
REGISTER
(1)
(CONTINUED)
Note 1: The RCFGCAL register is only affected by a POR.
2: A write to the RTCEN bit is only allowed when RTCWREN = 1.
3: This bit is read-only. It is cleared when the lower half of the MINSEC register is written.