Datasheet

© 2009-2012 Microchip Technology Inc. Preliminary DS70616F-page 45
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
bit 2 SFA: Stack Frame Active Status bit
1 = Stack frame is active. W14 and W15 address 0x0000 to 0xFFFF, regardless of DSRPAG and DSW-
PAG values
0 = Stack frame is not active. W14 and W15 address of EDS or Base Data Space
bit 1 RND: Rounding Mode Select bit
1 = Biased (conventional) rounding enabled
0 = Unbiased (convergent) rounding enabled
bit 0 IF: Integer or Fractional Multiplier Mode Select bit
1 = Integer mode enabled for DSP multiply
0 = Fractional mode enabled for DSP multiply
REGISTER 3-2: CORCON: CORE CONTROL REGISTER (CONTINUED)
Note 1: This bit is available on dsPIC33EPXXX(GP/MC/MU)806/810/814 devices only.
2: This bit is always read as ‘0’.
3: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.