Datasheet

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
DS70616F-page 416 Preliminary © 2009-2012 Microchip Technology Inc.
bit 7-5 SSRC<2:0>: Sample Clock Source Select bits
If SSRCG =
1:
111 = Reserved
110 = PWM Generator 7 primary trigger compare ends sampling and starts conversion
(2)
101 = PWM Generator 6 primary trigger compare ends sampling and starts conversion
(2)
100 = PWM Generator 5 primary trigger compare ends sampling and starts conversion
(2)
011 = PWM Generator 4 primary trigger compare ends sampling and starts conversion
(2)
010 = PWM Generator 3 primary trigger compare ends sampling and starts conversion
(2)
001 = PWM Generator 2 primary trigger compare ends sampling and starts conversion
(2)
000 = PWM Generator 1 primary trigger compare ends sampling and starts conversion
(2)
If SSRCG = 0:
111 = Internal counter ends sampling and starts conversion (auto-convert)
110 = Reserved
101 = PWM secondary Special Event Trigger ends sampling and starts conversion
(2)
100 = Timer5 compare ends sampling and starts conversion
011 = PWM primary Special Event Trigger ends sampling and starts conversion
(2)
010 = Timer3 compare ends sampling and starts conversion
001 = Active transition on the INT0 pin ends sampling and starts conversion
000 = Clearing the Sample bit (SAMP) ends sampling and starts conversion (Manual mode)
bit 4 SSRCG: Sample Clock Source Group bit
[See bits 7-5 for details.]
bit 3 SIMSAM: Simultaneous Sample Select bit (only applicable when CHPS<1:0> = 01 or 1x)
When AD12B = 1, SIMSAM is: U-0, Unimplemented, Read as ‘0’
1 = Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or
Samples CH0 and CH1 simultaneously (when CHPS<1:0> = 01)
0 = Samples multiple channels individually in sequence
bit 2 ASAM: ADC Sample Auto-Start bit
(3)
1 = Sampling begins immediately after last conversion. SAMP bit is auto-set.
0 = Sampling begins when SAMP bit is set
bit 1 SAMP: ADC Sample Enable bit
1 = ADC S&H amplifiers are sampling
0 = ADC S&H amplifiers are holding
If ASAM = 0, software can write ‘1’ to begin sampling. Automatically set by hardware if ASAM = 1.
If SSRC = 000, software can write ‘0’ to end sampling and start conversion. If SSRC ≠ 000,
automatically cleared by hardware to end sampling and start conversion.
bit 0 DONE: ADC Conversion Status bit
(3)
1 = ADC conversion cycle is completed.
0 = ADC conversion not started or in progress
Automatically set by hardware when A/D conversion is complete. Software can write ‘0’ to clear DONE
status (software not allowed to write ‘1’). Clearing this bit does NOT affect any operation in progress.
Automatically cleared by hardware at start of a new conversion.
REGISTER 23-1: ADxCON1: ADCx CONTROL REGISTER 1 (CONTINUED)
Note 1: This bit is only available in the ADC1 module. In the ADC2 module, this bit is unimplemented and is read
as ‘0’.
2: This setting is available in dsPIC33EPXXX(MC/MU)806/810/814 devices only.
3: Do not clear the DONE bit in software if ADC Sample Auto-Start is enabled (ASAM = 1).