Datasheet

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
DS70616F-page 414 Preliminary © 2009-2012 Microchip Technology Inc.
23.2 ADC Helpful Tips
1. The SMPI control bits in the ADxCON2
registers:
a) Determine when the ADC interrupt flag is
set and an interrupt is generated, if
enabled.
b) When the CSCNA bit in the ADxCON2 reg-
ister is set to ‘1’, this determines when the
ADC analog scan channel list defined in the
AD1CSSL/AD1CSSH registers starts over
from the beginning.
c) When the DMA peripheral is not used
(ADDMAEN = 0), this determines when the
ADC result buffer pointer to ADC1BUF0-
ADC1BUFF, gets reset back to the
beginning at ADC1BUF0.
d) When the DMA peripheral is used
(ADDMAEN = 1), this determines when the
DMA address pointer is incremented after a
sample/conversion operation. ADC1BUF0
is the only ADC buffer used in this mode.
The ADC result buffer pointer to
ADC1BUF0-ADC1BUFF gets reset back to
the beginning at ADC1BUF0. The DMA
address is incremented after completion of
every 32nd sample/conversion operation.
Conversion results are stored in the
ADC1BUF0 register for transfer to RAM
using DMA.
2. When the DMA module is disabled
(ADDMAEN = 0), the ADC has 16 result buffers.
ADC conversion results are stored sequentially
in ADC1BUF0-ADC1BUFF regardless of which
analog inputs are being used subject to the
SMPI bits and the condition described in 1c
above. There is no relationship between the
ANx input being measured and which ADC buf-
fer (ADC1BUF0-ADC1BUFF) that the
conversion results will be placed in.
3. When the DMA module is disabled
(ADDMAEN = 1), the ADC module has only 1
ADC result buffer, (i.e., ADC1BUF0), per ADC
peripheral and the ADC conversion result must
be read either by the CPU or DMA controller
before the next ADC conversion is complete to
avoid overwriting the previous value.
4. The DONE bit (ADxCON1<0>) is only cleared at
the start of each conversion and is set at the
completion of the conversion, but remains set
indefinitely even through the next sample phase
until the next conversion begins. If application
code is monitoring the DONE bit in any kind of
software loop, the user must consider this
behavior because the CPU code execution is
faster than the ADC. As a result, in manual sam-
ple mode, particularly where the users code is
setting the SAMP bit (ADxCON1<1>), the
DONE bit should also be cleared by the user
application just before setting the SAMP bit.
23.3 ADC Resources
Many useful resources related to Analog-to-Digital
Conversion are provided on the main product page of
the Microchip web site for the devices listed in this data
sheet. This product page, which can be accessed using
this link, contains the latest updates and additional
information.
23.3.1 KEY RESOURCES
• Section 16. “Analog-to-Digital Converter
(ADC)” (DS70621)
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All related dsPIC33E/PIC24E Family Reference
Manuals Sections
• Development Tools
Note: In the event you are not able to access the
product page using the link above, enter
this URL in your browser:
http://www.microchip.com/wwwproducts/
Devices.aspx?dDocName=en554310