Datasheet

© 2009-2012 Microchip Technology Inc. Preliminary DS70616F-page 383
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
22.0 USB ON-THE-GO (OTG)
MODULE (dsPIC33EPXXXMU8XX
AND PIC24EPGU8XX DEVICES
ONLY)
22.1 Overview
The Universal Serial Bus (USB) On-The-Go (OTG)
module includes the following features:
• USB full-speed support for host and device
• Low-speed host support
• USB On-The-Go support
• Integrated signaling resistors
• Integrated analog comparators for V
BUS
monitoring
• Integrated USB transceiver
• Hardware performs transaction handshaking
• Endpoint buffering anywhere in system RAM
• Integrated DMA controller to access system RAM
• Support for all four transfer types:
- Control
- Interrupt
- Bulk data
- Isochronous
• Queueing of up to four endpoint transfers without
servicing
• USB 5V charge pump controller
The USB module contains the analog and digital
components to provide a USB 2.0 full-speed and low-
speed embedded host, full-speed device, or OTG
implementation with a minimum of external
components.
The USB module consists of the clock generator, the
USB voltage comparators, the transceiver, the Serial
Interface Engine (SIE), pull-up and pull-down resistors,
and the register interface. Figure 22-1 illustrates the
block diagram of the USB OTG module.
The device auxiliary clock generator provides the 48
MHz clock required for USB communication. The
voltage comparators monitor the voltage on the V
BUS
pin to determine the state of the bus. The transceiver
provides the analog translation between the USB bus
and the digital logic. The SIE is a state machine that
transfers data to and from the endpoint buffers and
generates the protocol for data transfers. The
integrated pull-up and pull-down resistors eliminate the
need for external signaling components. The register
interface allows the CPU to configure and
communicate with the module.
22.1.1 Clearing USB OTG Interrupts
Unlike device level interrupts, the USB OTG interrupt
status flags are not freely writable in software. All USB
OTG flag bits are implemented as hardware set-only
bits. Additionally, these bits can only be cleared in
software by writing a ‘1’ to their locations (i.e.,
performing a BSET instruction). Writing a ‘0’ to a flag bit
(i.e., a BCLR instruction) has no effect.
Note 1: This data sheet is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 25. “USB On-
The-Go (OTG)” (DS70571) of the
“dsPIC33E/PIC24E Family Reference
Manual”, which is available from the
Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Note: The implementation and use of the USB
specifications and other third party
specifications or technology may require a
license from various entities, including,
but not limited to USB Implementers
Forum, Inc. (also referred to as USB-IF). It
is your responsibility to obtain more
information regarding any applicable
licensing obligations.
Note: Throughout this section, a bit that can only
be cleared by writing a ‘1’ to its location is
referred to as “Write ‘1’ to clear bit”. In reg-
ister descriptions, this function is indicated
by the descriptor, “K”.