Datasheet

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
DS70616F-page 38 Preliminary © 2009-2012 Microchip Technology Inc.
FIGURE 3-1: dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 CPU
BLOCK DIAGRAM
Power-up
Timer
Oscillator
Start-up Timer
Instruction
Decode and
Control
OSC1/CLKI
MCLR
VDD, VSS
UART1-
Timing
Generation
ECAN1,
16
PCH PCL
16
Program Counter
16-bit ALU
24
24
24
24
X Data Bus
IR
I2C1,
DCI
PCU
ADC1,
Timers
Input
Capture
Output
Compare
16
16
16
16 x 16
W Reg Array
Divide
Support
Engine
(1)
DSP
ROM Latch
16
Y Data Bus
(1)
EA MUX
X RAGU
X WAGU
Y AGU
(1)
AVDD, AVSS
UART4
SPI4
16
24
16
16
16
16
16
16
16
8
Interrupt
Controller
PSV and Table
Data Access
Control Block
Stack
Control
Logic
Loop
Control
Logic
Data LatchData Latch
Y Data
RAM
(1)
X Data
RAM
Address
Latch
Address
Latch
Control Signals
to Various Blocks
16
SPI1-
Data Latch
I/O Ports
16
16
16
X Address Bus
Y Address Bus
24
Literal Data
ADC2
Program Memory
Watchdog
Timer
POR/BOR
Address Latch
PMP
Comparator
CRC
RTCC
USB
I2C2
ECAN2
QEI1
(1)
,
PWM
(1)
QEI2
(1)
Note 1: This feature or peripheral is only available on dsPIC33EPXXX(MC/MU)806/810/814 devices.
2: This feature or peripheral is only available on dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU806/810/814 devices.
OTG
(2)