Datasheet

© 2009-2012 Microchip Technology Inc. Preliminary DS70616F-page 335
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
18.0 SERIAL PERIPHERAL
INTERFACE (SPI)
The SPI module is a synchronous serial interface use-
ful for communicating with other peripheral or micro-
controller devices. These peripheral devices can be
serial EEPROMs, shift registers, display drivers, A/D
converters, etc. The SPI module is compatible with
Motorola’s SPI and SIOP interfaces.
Four SPI modules are provided on a single device.
These modules, which are designated as SPI1, SPI2,
SPI3 and SPI4, are functionally identical with the excep-
tion that SPI2 is not remappable. The dedicated SDI2,
SDO2, and SCK2 connections provide improved perfor-
mance over SPI1, SPI3 and SPI4 (see
Section 32.0
“Electrical Characteristics”
). Each SPI module
includes an eight-word FIFO buffer and allows DMA bus
connections. When using the SPI module with DMA,
FIFO operation can be disabled.
The SPIx serial interface consists of four pins, as
follows:
• SDIx: Serial Data Input
• SDOx: Serial Data Output
• SCKx: Shift Clock Input or Output
• SSx/FSYNCx: Active-Low Slave Select or Frame
Synchronization I/O Pulse
The SPIx module can be configured to operate with
two, three or four pins. In 3-pin mode, SSx
is not used.
In 2-pin mode, neither SDOx nor SSx
is used.
Figure 18-1 illustrates the block diagram of the SPI
module in Standard and Enhanced modes.
FIGURE 18-1: SPIx MODULE BLOCK DIAGRAM
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXX(GP/MC/MU)806/
810/814 and PIC24EPXXX(GP/GU)810/
814 families of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 18. “Serial
Peripheral Interface (SPI)” (DS70569)
of the “dsPIC33E/PIC24E Family
Reference Manual”, which is available
from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Note: In this section, the SPI modules are
referred to together as SPIx, or separately
as SPI1, SPI2, SPI3 and SPI4. Special
Function Registers follow a similar nota-
tion. For example, SPIxCON refers to the
control register for the SPI1, SPI2, SPI3
or SPI4 module.
Internal Data Bus
SDIx
SDOx
SSx
/FSYNCx
SCKx
SPIxSR
bit 0
Shift
Control
Edge
Select
F
P
Primary
1:1/4/16/64
Enable
Prescaler
Secondary
Prescaler
1:1 to 1:8
Sync
Clock
Control
SPIxBUF
Control
Transfer
Transfer
Write SPIxBUF
Read SPIxBUF
16
SPIxCON1<1:0>
SPIxCON1<4:2>
Master Clock
8-Level FIFO
Transmit Buffer
(1)
8-Level FIFO
Receive Buffer
(1)
Note 1: In Standard mode, the FIFO is only one level deep.