Datasheet
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
DS70616F-page 322 Preliminary © 2009-2012 Microchip Technology Inc.
17.2 QEI Control Registers
REGISTER 17-1: QEIxCON: QEI CONTROL REGISTER
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
QEIEN
— QEISIDL PIMOD<2:0>
(1)
IMV<1:0>
(2)
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— INTDIV<2:0>
(3)
CNTPOL GATEN CCM<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 QEIEN: Quadrature Encoder Interface Module Counter Enable bit
1 = Module counters are enabled
0 = Module counters are disabled, but SFRs can be read or written to
bit 14 Unimplemented: Read as ‘0’
bit 13 QEISIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12-10 PIMOD<2:0>: Position Counter Initialization Mode Select bits
(1)
111 = Reserved
110 = Modulo count mode for position counter
101 = Resets the position counter when the position counter equals QEIxGEC register
100 = Second index event after home event initializes position counter with contents of QEIxIC
register
011 = First index event after home event initializes position counter with contents of QEIxIC register
010 = Next index input event initializes the position counter with contents of QEIxIC register
001 = Every Index input event resets the position counter
000 = Index input event does not affect position counter
bit 9-8 IMV<1:0>: Index Match Value bits
(2)
11 = Index match occurs when QEB = 1 and QEA = 1
10 = Index match occurs when QEB = 1 and QEA = 0
01 = Index match occurs when QEB = 0 and QEA = 1
00 = Index input event does not affect position counter
bit 7 Unimplemented: Read as ‘0’
Note 1: When CCM = 10 or CCM = 11, all of the QEI counters operate as timers and the PIMOD<2:0> bits are
ignored.
2: When CCM = 00 and QEA and QEB values match Index Match Value (IMV), the POSCNTH and
POSCNTL registers are reset.
3: The selected clock rate should be at least twice the expected maximum quadrature count rate.