Datasheet

© 2009-2012 Microchip Technology Inc. Preliminary DS70616F-page 301
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
REGISTER 16-8: SSEVTCMP: PWM SECONDARY SPECIAL EVENT COMPARE REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SSEVTCMP<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SSEVTCMP<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 SSEVTCMP<15:0>: Special Event Compare Count Value bits
REGISTER 16-9: CHOP: PWM CHOP CLOCK GENERATOR REGISTER
R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
CHPCLKEN
— — — — — CHOP<9:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CHOP<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CHPCLKEN: Enable Chop Clock Generator bit
1 = Chop clock generator is enabled
0 = Chop clock generator is disabled
bit 14-10 Unimplemented: Read as ‘0’
bit 9-0 CHOP<9:0>: Chop Clock Divider bits
The frequency of the chop clock signal is given by the following expression:
Chop Frequency = F
PWM/(CHOP<9:0> + 1)
Where, FPWM is FP divided by value based on the PCLKDIV settings.