Datasheet

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
DS70616F-page 188 Preliminary © 2009-2012 Microchip Technology Inc.
REGISTER 9-6: ACLKDIV3: AUXILIARY CLOCK DIVISOR REGISTER 3
(1,2)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — APLLDIV<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-3 Unimplemented: Read as ‘0’
bit 2-0 APLLDIV<2:0>: PLL Feedback Divisor bits (PLL Multiplier Ratio)
111 = 24
110 = 21
101 = 20
100 = 19
011 = 18
010 = 17
001 = 16
000 = 15 (default)
Note 1: This register resets only on a Power-on Reset (POR).
2: This register is only available on dsPIC33EPXXXMU8XX and PIC24EPXXXGU8XX devices.