Datasheet

© 2009-2012 Microchip Technology Inc. Preliminary DS70616F-page 187
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
REGISTER 9-5: ACLKCON3: AUXILIARY CLOCK CONTROL REGISTER 3
(1,2)
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0
ENAPLL
— SELACLK AOSCMD<1:0> ASRCSEL FRCSEL —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0
APLLPOST<2:0>
— — APLLPRE<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ENAPLL: Enable Auxiliary PLL (APLL) and Select APLL as USB Clock Source bit
1 = APLL is enabled, the USB clock source is the APLL output
0 = APLL is disabled, the USB clock source is the input clock to the APLL
bit 14 Unimplemented: Read as ‘0’
bit 13 SELACLK: Select Auxiliary Clock Source for Auxiliary Clock Divider bit
1 = Auxiliary PLL or oscillator provides the source clock for auxiliary clock divider
0 = Primary PLL provides the source clock for auxiliary clock divider
bit 12-11 AOSCMD<1:0>: Auxiliary Oscillator Mode bits
11 = EC (External Clock) mode select
10 = XT (Crystal) Oscillator mode select
01 = HS (High-Speed) Oscillator mode select
00 = Auxiliary Oscillator Disabled (default)
bit 10 ASRCSEL: Select Reference Clock Source for APLL bit
1 = Primary Oscillator is the clock source for APLL
0 = Auxiliary Oscillator is the clock source for APLL
bit 9 FRCSEL: Select FRC as Reference Clock Source for APLL bit
1 = FRC is clock source for APLL
0 = Auxiliary oscillator or Primary Oscillator is the clock source for APLL (determined by ASRCSEL bit)
bit 8 Unimplemented: Read as ‘0’
bit 7-5 APLLPOST<2:0>: Select PLL VCO Output Divider bits
111 = Divided by 1
110 = Divided by 2
101 = Divided by 4
100 = Divided by 8
011 = Divided by 16
010 = Divided by 32
001 = Divided by 64
000 = Divided by 256 (default)
bit 4-3 Unimplemented: Read as ‘0’
bit 2-0 APLLPRE<2:0>: PLL Phase Detector Input Divider bits
111 = Divided by 12
110 = Divided by 10
101 = Divided by 6
100 = Divided by 5
011 = Divided by 4
010 = Divided by 3
001 = Divided by 2
000
= Divided by 1 (default)
Note 1: This register resets only on a Power-on Reset (POR).
2: This register is only available on dsPIC33EPXXXMU8XX and PIC24EPXXXGU8XX devices.