Datasheet

© 2009-2012 Microchip Technology Inc. Preliminary DS70616F-page 179
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
Figure 9-3 illustrates a block diagram of the Auxiliary
PLL module.
FIGURE 9-3: APLL BLOCK DIAGRAM
Equation 9-4 shows the relationship between the
Auxiliary PLL input clock frequency (FAIN) and the
A
VCO frequency (FAVCO).
EQUATION 9-4: AFVCO CALCULATION
TABLE 9-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION
Note: The Auxiliary PLL module is only available
on dsPIC33EPXXXMU8XX and
PIC24EPXXXGU8XX devices.
÷ N1
÷ M
PFD VCO
APLLPRE<2:0>
APLLDIV <2:0>
3 MHz < FAREF < 5.5 MHz
60 MH
Z < FAVCO < 120 MHZ
FAIN
FAREF
FAVCO
FAVCO FAIN
M
N1
-------
⎝⎠
⎛⎞
×=
Oscillator Mode
Oscillator
Source
POSCMD<1:0> FNOSC<2:0>
See
Note
Fast RC Oscillator with Divide-by-N (FRCDIVN) Internal xx 111 1, 2
Fast RC Oscillator with Divide-by-16 (FRCDIV16)
Internal xx 110 1
Low-Power RC Oscillator (LPRC) Internal xx 101 1
Secondary (Timer1) Oscillator (SOSC) Secondary xx 100 1
Primary Oscillator (HS) with PLL (HSPLL) Primary 10 011 —
Primary Oscillator (XT) with PLL (XTPLL) Primary 01 011 —
Primary Oscillator (EC) with PLL (ECPLL) Primary 00 011 1
Primary Oscillator (HS) Primary 10 010 —
Primary Oscillator (XT) Primary 01 010 —
Primary Oscillator (EC) Primary 00 010 1
Fast RC Oscillator (FRC) with Divide-by-N and PLL
(FRCPLL)
Internal xx 001 1
Fast RC Oscillator (FRC) Internal xx 000 1
Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit.
2: This is the default oscillator mode for an unprogrammed (erased) device.