Datasheet

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
DS70616F-page 178 Preliminary © 2009-2012 Microchip Technology Inc.
9.1 CPU Clocking System
The dsPIC33EPXXX(GP/MC/MU)806/810/814 and
PIC24EPXXX(GP/GU)810/814 family of devices
provide seven system clock options:
• Fast RC (FRC) Oscillator
• FRC Oscillator with Phase-Locked Loop (PLL)
• Primary (XT, HS or EC) Oscillator
• Primary Oscillator with PLL
• Secondary (LP) Oscillator
• Low-Power RC (LPRC) Oscillator
• FRC Oscillator with postscaler
Instruction execution speed or device operating
frequency, F
CY, is given by Equation 9-1.
EQUATION 9-1: DEVICE OPERATING
FREQUENCY
Figure 9-2 is a block diagram of the PLL module.
Equation 9-2 provides the relation between input
frequency (F
IN) and output frequency (FOSC).
Equation 9-3 provides the relation between input
frequency (F
IN) and VCO frequency (FVCO).
FIGURE 9-2: PLL BLOCK DIAGRAM
EQUATION 9-2: F
OSC CALCULATION
EQUATION 9-3: F
VCO CALCULATION
FCY = Fosc/2
÷ N1
÷
M
÷
N2
PFD VCO
PLLPRE<4:0>
PLLDIV<8:0>
PLLPOST<2:0>
0.8 MHz < FREF < 8.0 MHz
120 MH
Z < FVCO < 340 MHZ
FOSC < 120 MHz @ +125ºC
F
IN FREF FVCO FOSC
FOSC < 140 MHz @ +85ºC
FOSC FIN
M
N1 N2×
----------------------
⎝⎠
⎛⎞
× FIN
PLLDIV 2+()
PLLPRE 2+()2 PLLPOST 1+()×
-----------------------------------------------------------------------------------------
⎝⎠
⎛⎞
×==
Where,
N1 = PLLPRE + 2
N2 = 2 x (PLLPOST + 1)
M = PLLDIV + 2
FVCO FIN
M
N1
-------
⎝⎠
⎛⎞
× FIN
PLLDIV 2+()
PLLPRE 2+()
-------------------------------------
⎝⎠
⎛⎞
×==